This collaboration, IMEC and Synopsys said, aims to accelerate the development of TSV technologies and to facilitate the adoption of 3D stacked ICs in the semiconductor industry.

The collaborative research is taking place at IMEC, where silicon wafers with test structures are manufactured and tested. Synopsys' TCAD tools are used to model the TSVs in the chip stacks to optimize 3D stacked IC performance and reliability.

Earlier this week, IMEC unveiled a collaboration agreement with Altos Design Automation Inc. (San Jose, Calif.) to provide re-characterization of standard foundry or library vendor libraries including core and IO cells at different process, temperatures and/or voltages.

Through the collaboration, IMEC said it has extended its ASIC prototyping and volume fabrication service with library re-characterization. This is essential when designing in 65nm and 40nm nodes.