Startup proposes SOI JFETs for low power

LONDON — SuVolta Inc. (Los Gatos, Calif.), a startup formerly known as DSM Solutions Inc., has revealed some details of the company's plan to achieve low power IC operation through the use of complementary junction FET technology.

Ashok Kapoor, CTO of SuVolta, made a presentation at the 2010 CMOS Emerging Technologies Workshop held in Whistler, British Columbia, May 19 to 21. In this case CMOS stands for communications, Microsystems, optoelectronics and sensors. Kapoor's presentation was variously entitled "VLSI with complementary JFET" and "JFET technology for very low power." The lateral junction FET differs from a MOSFET in that it uses a reverse-biased p-n junction to separate the gate from the body of the transistor, rather than an insulation layer. Also its channel doping is the same as the doping of its source and drain creating similarities in operation to proposed junction-less nanowire transistors.

Kapoor was part of the team of founders that formed DSM Solutions in 2005. The company has raised $25 million since then and taken on to its board of directors Bill Joy and Andy Rappaport to represent the interests of venture capital firms Kleiner Perkins Caufield & Byers and August Capital, respectively. SuVolta raised $3 million in December 2009, by which time the company had changed its name to SuVolta and Bruce McWilliams, former chairman, president and CEO of chip packaging company Tessera Technologies Inc. (San Jose, Calif.), had joined as CEO. The company has been granted a number of patents on the use of JFET technology for low-power logic, memory and signaling.

In his Whistler presentation Kapoor proposed the use of a double-gated JFET as it has a near-ideal sub-threshold swing. He gave measurements for NFET and PFET structures built with a 60-nm gate.

Kapoor also showed results for 99-stage ring oscillator built with complementary JFETs on bulk silicon. He also discussed the drawbacks of high p-well capacitance and the area penalty incurred to isolate transistors for JFETs implemented in bulk silicon. Kapoor's proposed solution is to build complementary JFETs on a silicon-on-insulator (SOI) substrate.

In his summary to the Whistler presentation Kapoor said: "Subsequently, functional logic circuits made with JFET on SOI have also been demonstrated." He concluded: "JFET operation has been simulated for channel length below 20-nm with reasonable Ion/Ioff ratio for voltage supply of 0.5V, making it a candidate for scaling to shorter dimensions."

Jeff Lewis, recently-appointed vice president of marketing and business development, said SuVolta is "developing a variety of technologies and methodologies for significantly lowering semiconductor power consumption." Lewis also told EE Times: "We are not going to make our own chips; instead we will make the technology available to others so they may include it in their own products."

More information about SuVolta can be obtained from peter.clarke@ubm.com.

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