IBM, partners to report 22-nm FinFET SRAM

The authors are due to present a paper at the Symposium on VLSI Technology to be held in Honolulu, Hawaii, from June 15 to 17.

The authors claim the cell area produced by their work is the smallest SRAM cell produced using optical lithography. It is fabricated with a gate pitch of 80-nm and a fin pitch of 40-nm and is shown to be intended for the 22-nm node.

The cell is operational down to supply voltage of 0.4-V. A double-expose, double-etch (DE2) sidewall image transfer (SIT) process is used to produce the fins.

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