ADRES processor moving to 40-nm
"We got rid of the central bus [of previous platforms] in favor of a crossbar architecture. We are also upgrading ADRES," said Liesbet Van Der Perre, program director for wireless communication.
The third iteration of ADRES will include instruction-, data- and task-level parallelism backed up by the DRESC compiler. ADRES thus features multi-threading and wide SIMD capabilities. The associated tools enable C-based compilation, as well as assisted parallelization over multiple cores and/or threads. This speeds up the design leading to shorter time-to-market and more energy-efficient radios.
The ability to use compilation tools and yet still produce power-efficient algorithm execution is key according to Van Der Perre because of the need to continuously target new protocols as they are brought forward by the industry. An inability to do this with some commercial software-defined radios could cause huge resource costs coding and testing at a deep level, she said.
IMEC has added to the platform a flexible forward-error correction (FlexFEC) processor template achieving high-speed turbo and low-density parity check (LDPC) is also included. An LDPC-specific instance for multi-standard broadcasting has also been derived to further optimize power and area. Moreover, Cobra features an ASIP-based digital front-end enabling flexible filtering synchronization and spectrum sensing. This component also enables hierarchical platform activation, resulting in idle power in the range of 2-mW in 65-nm low-power CMOS technology for the baseband platform.
The Cobra platform is now available for licensing. The reconfigurable radio architecture and related cores can be evaluated and tested at IMEC and the research institute is in the process of committing its third-generation ADRES processor to silicon on a 40-nm CMOS process. However, when asked about the tape-out for the processor, Van Der Perre said: "Not in 2010."
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The software defined radio flexible air interface by Liesbet Van Der Perre