TSMC, Tela trim logic die area by 15%

LONDON — Taiwan Semiconductor Manufacturing Co. Ltd. has introduced its so-called Slim Library of standard cells, which reduces system-on-chip (SoC) routed logic block area by 15 percent compared to blocks routed through conventional standard cell libraries.

The library, developed as a result of a collaboration between TSMC (Hsinchu, Taiwan) and Tela Innovations Inc. (Los Gatos, Calif.), targets TSMC's 65-nm LP process technology. Designers can use the Slim Library in existing or new designs without change to design tools and implementation methodologies.

The two companies did not say if or when the Slim Library approach would be applied to 45, 40, or 28-nm manufacturing processes.

The Tela layout style draws a pattern with uniform density through unidirectional polycrystalline silicon on a fixed pitch with improved manufacturing process control to reduce area. As a result, Slim Library achieves gate densities of up to 1 million gates per square millimeter. The two companies have demonstrated the 15 percent area improvement through synthesis and timing-driven place-and-route implementations on multiple versions of widely-used microprocessor cores.

Slim Library re-designs into 8 tracks what has traditionally been a 9-track configuration, TSMC said. The library includes multiple threshold voltage options and power management cells along with full set of characterization corners.

The 65LP Slim Library is available now to a limited set of customers. General release is scheduled for the first quarter of 2011.

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