News & Analysis
Toshiba reports 16-nm nanowire transistor
Peter Clarke
6/15/2010 8:48 AM EDT
The company said it has achieved 1-mA per micron on-current, the world's highest level for a nanowire transistor, by reducing parasitic resistance and improving the on-current level by 75 percent. The work is due to be presented at the 2010 Symposium on VLSI Technology in Hawaii, on June 17.
It is well-understood that as planar transistors scale to smaller dimensions current leakage between source and drain in the off-state becomes a critical problem. To get round this chip companies have investigated 3-D structures to increase the gate area, such as FinFETs where the gate wraps around three-sides of the channel.
The silicon nanowire transistor can suppress off-leakage and achieve further short-channel operation, because its thin wire-shaped silicon channel (nanowire channel) is effectively controlled by the surrounding gate. However, parasitic resistance in the nanowire-shaped source/drain, especially in the region under the gate sidewall, degrades the on-current. Toshiba claims to have overcome this problem by optimizing gate fabrication and significantly reducing the thickness of the gate sidewall, from 30-nm to 10-nm. Low parasitic resistance was realized by epitaxial silicon growth on the source/drain with a thin gate sidewall, which leads to a 40 percent increase in on-current. The company also achieved a further 25 percent increase in current performance by changing the direction of the silicon nanowire channel from the <110> to <100> crystal plane direction.
The silicon nanowire transistor has an on-current of 1-mA per micron while the off-current is 100-microamps per micron, a 75 percent increase in the on-current at the same off-current condition.
Related links and articles:
SMIC, Macronix present copper-based resistive RAMs
Junctionless transistor is ready for 20-nm node, says researcher
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