Equalization, encoding details
The version 0.71 of the spec, released in early June, details changes needed in the training sequence to properly balance a dc transmission to derive a signal clock. It also makes it explicit engineers will have to use at least one tap of decision feedback equalization (DFE) in the receiver and three taps of continuous linear equalization in the transmitter.
Gennum Corp. announced in 2009 it is licensing silicon controller and physical-layer blocks for PCIe 3.0 that use five-tap DFE.
High end communications chips have implemented multiple levels of equalization for some time. However, the technology is new to the mainstream PC chip and board vendors that are the big users of PCI Express.
By comparison, the first version of PCIe supports data rates up to 2.5 GHz and used a single static level of signal de-emphasis. The second generation spec runs at up to 5 GHz and uses two levels of de-emphasis.
The 3.0 generation of Express is the first to use DFE and a dynamic feature where transmitters and receivers negotiate levels of signal de-emphasis at boot-up time. It is also the first version of Express to move from 8b/10b encoding to the more complex but efficient 128b/130b method.
At speeds up to 8 GHz, effects from the quality of the channel carrying the signal also come into play. To deal with such issues, the PCI SIG will release example S parameters describing a PCIe 3.0 channel and a basic open source tool to test channels for the interface. It's the first time the PCI SIG has released such tools.
"Before you release the design of your motherboard, you can be sure it will work," said Yanes. "We are trying to ensure things will go smoothly," he said.
PCI Express 3.0 is designed to be backward compatible with earlier versions of the spec and will run over two connectors and 20 inches of board traces. Yanes expects it will require at least 65nm process technology, and many will use 45nm.
Product testing will officially begin early next year. The PCI SIG will publish a list of compliant products starting in the fall of 2011.
"There are some [PCIe 3.0] products out there right now, but we aren’t going to publically endorse a product until our testing is done," said Yanes.
"Between our 0.7 and 0.9 versions of the specs there have been in the past some changes that impact silicon, but if people speculatively implement products that’s the risk they take," said Ramin. "Between the 0.9 and 1.0 versions, there won't be any changes impacting silicon," he added.
More than one of the PCI SIG member companies have developed test chips for PCIe 3.0. Some data from those test chips has been shared within a 3.0 working group to verify the specifications.
"As soon as the ink dries on the final 3.0 spec, we will look at new initiatives, but for 2010 and a good chunk of 2011 we are focused on getting out 3.0 compliant products," said Ramin. "At next year's dev con, we will have more to say about what's beyond 3.0," he added.
Intel has demonstrated research in September on optical interconnects expected to be the future for what comes beyond the next-generation of the USB bus.