Forum tries to spark standards for 3-D chips

SAN FRANCISCO--A group of about 60 engineers gathered at a Semicon West 2010 workshop here to take the first crack at outlining standards needed for 3-D silicon chips.

Linking stacks of chips with tiny silicon vias promises smaller devices that need less power to deliver greater performance for a variety of applications. But engineers said a wide range of standards are needed to design and make such chips.

Researchers said no show-stopping technical hurdles stand in the way of creating the so-called through-silicon vias. But there are multiple approaches to designing and making such chips, yields are still low and costs are high—problems standards can address.

"Hopefully we can kick off key working groups to start developing some standards," said Urmi Ray a senior staff engineer at Qualcomm who organized the workshop and helped develop prototype 3-D chips for cellphones. "We want the technology to be adopted quickly so we can get to revenue," she said

"We think there is a strong need for some form of standardization to accelerate the adoption of the technology and lead to cost reduction," said Arifur Rahman, a principal engineer at Xilinx who outlined in a keynote talk some of the areas to address.

Rahman said engineers need a full chip-to-chip interface standard that could be similar to the Jedec standard for a wide I/O DRAM interface. The stacks may use thousands of the links, some less than 25 microns long carrying data at Gbits/second rates.

Designers also need interoperable EDA tools that take into account stacks using chips made in different process technologies, he said.

In manufacturing, 3-D chips require standards in silicon wafers, chip materials and fab processes. A metrology engineer at Sematech described two dozen standards that need to be redefined to modify fab tools or processes for 3-D ICs.

"If you are going to do this stuff I strongly recommend you take your tools out for a test drive, but you can use standard 300mm tools," said Andy Rudack, a Sematech researcher in 3-D interconnects at the Albany, New York research lab.

Sematech has run bare 300mm wafers though a set of fab process tools including some packaging tools which have never been used in a fab clean room. Next year it expects to run fully processed 130nm or 65nm wafers through a 3-D process.

"When we first started 3-D processing, wafers were showing up broken or chipped," Rudack said. "I am now violating Sematech standards about 25 times a day," he quipped.

Wafer bonding and thinning processes used to make 3-D ICs create wafers that are larger or smaller than the Sematech M1.15 standard for 300mm wafers. As a result 3-D wafers can be heavier or different in size than robotic systems expect.

The thinning processes can also remove wafer ID information and alter notches used for handling wafers, he said.

New test standards are also needed, many of them potentially relying on new monitoring and inspection methods built into the chips. Due to their tiny size, "you may not be able to test through silicon vias directly and electrically," Rahman of Xilinx said.

New standards could also address when 3-D chips are tested and how the chips are handled and shipped at various points in the semiconductor supply chain, Rahman said.

Today engineers use wire bonding using less than a hundred tiny wires making interconnects around the outside of a stacks of similar kinds of chips such as NAND and DRAM chips. The new 3-D chips could link at higher data rates different kinds of digital and analog logic and memory chips made in different processes.

"We are beginning to see deployment of the technology in CMOS sensors, so we are entering early adoption stage, but to jump to broader acceptance we need to make this compelling for more apps," he said.