Samsung, Toshiba agree to set DDR NAND standard

LONDON — Samsung and Toshiba have announced they will develop a second-generation double data rate (DDR) NAND flash memory specification with a 400-Mbit/s interface. The companies did not say when a device built to the specification would be available or what memory capacity it would have.

The DDR 2.0 NAND memory is expected to be benefit mobile and consumer electronics applications.

The current toggle DDR 1.0 specification applies a DDR interface to conventional single data rate NAND architecture. The resulting NAND chip has a 133-Mbit per second interface. Samsung and Toshiba said they will focus on developing a 400-Mbit per second interface for the toggle DDR 2.0 specification, which provides ten-fold increase over 40-Mbit per second SDR NAND in widespread use today.

The two companies started participating in standardization efforts for DDR 2.0 through the JEDEC Solid State Technology Association, last month.

"Our introduction of high-speed 30-nanometer class NAND late last year served as an initial pathway for stimulating acceptance of the new high-performance toggle DDR technology," said Dong-Soo Jun, executive vice president of memory marketing at Samsung Electronics Co. Ltd. (Seoul, South Korea), in a statement. "The rapid adoption of fourth generation (4G) smartphones, tablet PCs and solid state drives is expected to drive demand for a broader range of high-performance NAND solutions."

"Toggle DDR provides a faster interface than conventional NAND using an asynchronous design, delivering the benefits of high-speed data transfer to a wider market, such as for solid state drive applications including enterprise storage, mobile phones, multimedia terminals and consumer products," said Masaki Momodomi, memory product technical executive with Toshiba, in the same statement. 

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