Phase-change memory: A rebuttal of Micron’s article

8/5/2010 7:39 AM EDT

Mr. Neale,
I want to congratulate you for the first lucid analysis of PCM ever published. For those who want the impossible, the heat transfer of a hot bit like that would require the properties of molten sodium. So, never mind the power scalability, the ability to get heat out is already compromised at any level. The only memory left in a small area is the "memory" of delaminated electrodes. Now for those enlightened souls who propose "quantum Mechanics" to describe crystallization, here are a couple of pointers: (1) Quantum effects in this case are for electrons, not atoms;(2)Atoms going to a solid state structural phase transition are classical (h=0), hardly a place to put a wave function in.

8/3/2010 1:27 AM EDT

I love that kind of talk.

8/10/2010 10:56 AM EDT

As pointed out by Neale’s rebuttal, the current density of the array access device is also of critical concern in scaling PCM, however the alarm for MOS device drive capability is irrelevant for high density stand alone PCM arrays as Samsung, Hynix and Numonyx have selected either a bipolar or diode select devices. I would suggest that readers refer to a 2010 IEEE peer reviewed paper where “it was shown that no effect on BJT and storage element reliability is expected in scaled BJT-PCM architectures down to the 16 nm technology node” [3].

Neale’s follow-up comments that PCM must move to the 1x and 2x nm generations to be competitive ignores the sequential path for PCM to initially achieve success at the 4X nm generation by addressing NOR applications (still a multi-billion $ market) -- followed by a higher level of success in the 3X nm generation. At this generation, PCM will have a significant cost advantage over NOR and it can selectively displace DRAM based on its lower power, equivalent to lower cost and sufficient cycle and speed performance for a given application -- enabling instant-on applications in smart phones followed by instant-on tablets, net books and sub notebooks, etc.

NOR has a 10-12F2 cell size and DRAM has a 6-8 F2 cell size and will always be SLC whereas PCM cell size is 4-6 F2 with eventual MLC capability [4]. Because of the simplicity of the PCM device structure – PCM has already passed both DRAM and NOR in being further along in demonstrating working cells at the 16-17 nm technology node [1,2].

[4] Y.N. Hwang, et al., “MLC PRAM with SLC Write-speed and Robust Read Scheme,” 2010 Symposium on VLSI Technology Digest of Technical Papers (2010).

8/10/2010 11:16 AM EDT

Is the requirement for diode or bjt selector a liability? A small F^2 factor doesn't mean lower cost if you add more process complexity.

8/16/2010 4:48 PM EDT

Ex-DRAMer-The question remains with respect to reliability how safe are the current densities of 4.5 X 10E7 A/sq-cm and 6.3 X10E7 A/sq-cm that you cite. (I can add that my calculation, based on published data, suggest that Numonyx with the 45nm, 1 Gbit array appear to have managed to keep current density of the level 1to2x10E7Amps/sq-cm).
More specifically what is the effect of those current densities on molten chalcogenide, or hot heater/contacts. Is molten chalcogenide the rare material free from the effects of electro-migration. Especially composition changes in the direction of current flow, and its consequences. To rely on, sometimes questionable, two terminal device measurements without knowledge of what is really happening, when pushing current density boundaries, is perhaps not the safest path to product success.
Rather than trying to negate discussion with claims of peer group review, perhaps you could cite the source of literature on electromigration effects in chalcogenides and any other materials, at the current densities above.
Without giving too much away, I should say that for some time I have been taking all the published results of PCM current density, for link, pore and dome structures and have been plotting them on a single graph. I have been adding new results as they have been published, plus private communications from companies involved. The conclusions provide interesting possible view of the PCM future.
This was to be part of my paper at NVMS2009, "PCM Scalability-Myth or Realistic Device Projection" but I was unable to travel at the time. I understand a new version of that paper will be published in EETimes shortly, including all the graphical data.
With respect to write/erase lifetime positive high number results were reported right from the start for a few devices and for a variety of demonstration devices, under conditions that are very selective.

8/16/2010 4:57 PM EDT

I think the claims for billions of dollars of sales when you replace Flash NOR with PCM at 3xnm or 4xnm. Will rely on serious competitive PCM product in the market place now, where are they? Other wise, with respect, I think you are just indulging in marketing hype.
Throughout the history of PCM development, I am afraid "WORKING CELLS", even those test cells from arrays have developed a habit of not becoming price and performance competitive PCM array products.

8/16/2010 9:32 PM EDT

Prior to publishing your article I suggest that you revisit your methodology for calculating current density because your ‘suggested’ “1to2x10E7Amps/sq-cm” for Numonyx 1 Gb 45 nm is low by a factor of 6-10 based on Numonyx’s published current density for their 45 nm technology. See figure 12 from previous cited reference where the device endurance is reported as a function of programming current density for their 180, 90 and 45 nm PCM technology nodes [3]. In the previously cited reference by Samsung the cycle endurance was reported at 1x10E11 cycles for the reported 6.3 X10E7 A/sq-cm [1].

In both the cited Numonyx and Samsung PCM technologies the PCM active region of the storage element is realized by the intersection of a lithographic feature with a deposited thin film heater that can be in the range of 10 times smaller than the lithographic capability [1.3,5]

It was never claimed that Chalcogenide nor the electrodes utilized in PCM cells are rare materials free from the effects of electromigration. There have been numerous articles published on failure analysis of cycle life failures in PCM and they show electromigration / compositional changes are indeed the dominant failure mode, but the failures occur at cycle endurance values well past current flash cycle endurance values. As stated and cited previously “no impact is observed (for cycling endurance) on scaled devices where the higher current density values are needed to reach the same GST melting temperature” [3].

As the PCM cell type migrates with scaling to a confined (constrained) cell the high temperature molten phase change volume is moved away from the electrodes minimizing the temperature at the electrode phase change layer interface leading to significantly enhanced cycle endurance of greater 1x10E10 to 1x10E11 [1,5].

[5] D.H. Im et al.,” A Unified 7.5nm Dash-Type Confined Cell for High Performance PRAM Device” IEDM Tech. Dig., p. 211 , 2008

8/16/2010 9:39 PM EDT

I don’t have a crystal ball and never intended to estimate when PCM will be “billions of dollars of sales”. My main point was that PCM does not need wait until 1x or 2x production to enter the market place. It is a simple statement of fact that the NOR market has not disappeared and is still today a multi-billon dollar market. I believe a realsitic estimate for PCM market valuation was given by a Samsung interview in The Korea Herald:
“Memory for portable consumer devices today is at a major turning point as mobile applications increasingly require more diverse memory technology,” said Jun Dong-soo, an executive vice president at Samsung Electronics.

“The launch of our PRAM in an advanced MCP solution for the replacement of 40 nm-class and finer geometry NOR meets this need head-on,” he said.

Samsung plans to increase the lineup of its large-capacity, high-performance PRAM products and expand PRAM applications to other mobile devices such as MP3 players, portable multimedia players and navigational devices, as well as solid state drives and HDTVs.

Samsung expected the global PRAM market to reach $10 million this year and grow to $120 million in 2011, $350 million in 2012 “ [6] The sales of PCM in this timeframe will be on technology greater than 1x-2X nodes. Note the initial PRAM application in MP3 players and solid state drives is not to displace NAND, but rather to act a low latency buffer in the SSD / MP3 memory hierarchy enhancing the system level performance.

[6] “Samsung supplies first PRAM for handsets” The Korea Herald 2010-04-28 http://www.koreaherald.com/national/Detail.jsp?newsMLId=20100428000630

8/16/2010 10:01 PM EDT

ex-DRAMer mentioned: "As the PCM cell type migrates with scaling to a confined (constrained) cell the high temperature molten phase change volume is moved away from the electrodes minimizing the temperature at the electrode phase change layer interface leading to significantly enhanced cycle endurance of greater 1x10E10 to 1x10E11 " We have tried this and found the confining approach definitely reduces the RESET current and theoretically reduces SET time. However, due to the longer strip of higher resistance of the confining section, the operation voltage increases. It was the opposite trend of the expectation of DRAM makers and foundries. For Flash makers, it was okay. But the power consumption for PCM is larger than for flash. So we could not make the larger number of cycles appear attractive. The last feature we tried to grab was MLC, but this is defeated even with limited temperature range when you consider the resistance drift.

8/17/2010 11:15 AM EDT

Some additional thoughts:
Coming with one or several reliable disruptive approaches for memories do not hurt as the technologies currently used in Flash ,
for storage or execute in place, and DRAM are reaching road blocks. Having watched the PCM for a long time, and I happend to have worked for Intel
where I could not understand the need for PCM while NAND and NOR still have plenty of room for scalability.
I do not believe that one can claim victory or making claims as reported the last decade or so, mainly by Intel/Numonyx.
With all the claims one would think there must be "some volume manufacturing of PCM"!

8/17/2010 11:16 AM EDT

While the concept of "phase change in some materials such as colcogenide materials" leading to "distinct resistive states",
was brilliant (several decades ago) it could not in any ways compete with current flash. Those who preached for PCM,
wanted to displace current Flash they do not master well the art (current flash technology that is). Current Flash continued to scale until today. Current Flash allows precise charge trapping in floating gate.
This precise control of charge led to Multiple Bits per cell. PCM would have hard time accomodating Multiple Bits per cell as excessive temperature (600C for programming) and material consistency (due to electromigration and other) "may" get in the way.
Therefore, I do not believe one can adjust the cell resistance that easy considering the melten material. In addition, considering chip thermal capacitance and poor thermal conductivity of materials such as oxide in isolation or oxide/nitride used for
passivations, or package, cell temperature will not drop that easy as claimed in the past (few nanoseconds)! Perhaps true in the open air.
In the package, some sort of heat dissipators may be needed to prevent "thermal build-up" that can raise junction temperature leading to inacceptable leakage that may push the silicon toward intrinsec regime. Furthermore, one has to have distinct programmed / erased windows. The resistance associated with these windows must be relatively high so it is not easily affected by parasitic resistances (contact, interconnect, etc.). Therefore, one must rely on, relatively speaking, power devices (high current coupled with high voltage) to enable adequat programming.
Finally, from what I see all along, I consider the PCM a laboratory curiosity and it is outdated. It could have had a place in history several decades ago, but short lived! Doing R&D on thing like PCM is fine, but for several decades at the expense of investors is wrong!

8/17/2010 10:16 AM EDT

CORRECTION To convey the intended sense please replace "Low" with "High" in the following paragraph.

Low number laboratory demonstrations of PCM w/e life times, have been difficult to turn into reliable PCM array products.

8/17/2010 10:24 AM EDT

I hope Mr. Atwood who is missing from this discussion is paying attention to these details in this blog.So he does not compromise employees and Micron investors welfare!

8/17/2010 1:42 PM EDT

As a correction - I never suggested that Numonyx had a range of current density from “6 x 10E7Amps/sq-cm to 2 x10E8Amps/sq-cm”. I stated that the range of current you gave was low by a factor of 6-10 and gave the reference to a figure and paper that showed an operating current density of 1.3 X10E8 Amps/sq-cm for the 45 nm node [3]. I should have more precisely stated that the current density range you were giving was low by a factor of 6.5 - 13.


In regards to calculating current density - it is not a question on being on the generous side or erring on the safe side “for fairness” – it is a matter of understanding the geometry of and structure of the PCM cell and utilizing a correct methodology to calculate the actual current density. In the all the recent PCM cell structures by Samsung, Hynix, Numonyx and IBM/Macronix a form of sub-lithographic technique (or ebeam in the case of the IBM line cell) is utilized to reduce the PCM storage area. The proposed sub-litho methods vary drastically and for a given cell technology and one can debate the manufacturability / scalability and controllability of the individual technique. However, it is erroneous to ignore the underlying device structure and associated sub litho technique incorporated in the cell construction in any meaningful current density calculation used to compare different cell technologies and geometries