Mentor moves tools toward 16-nanometer

A conversation last Friday (Aug. 20) with Joseph Sawicki, vice president and general manager of the Mentor Graphics Corp.'s Design to Silicon Division, provided a snapshot of the conundra facing foundries and EDA vendors as they approach sub-20-nm process geometries. The landscape is filled with uncertainties, Sawicki warned, but there is no time left to wait for resolution.

"We saw our first 16-nm test chips go out a couple of months ago," Sawicki said in an interview Friday (Aug. 20). "There is design work going on now at that node—so far, though, it is mostly intellectual-property development."

Sawicki cited some big bets that foundries and design teams are being forced to put on the table. One is the choice of gate-first or gate-last processing for high-k/metal-gate gate stacks. "It seems clear that gate-first will provide greater density," Sawicki said, but he warned that other uncertainties remain, such as potential differences in process variations and even whether both approaches will scale below 20-nm.

The questions are critical to chip designers because the two major foundry powers—Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) and Globalfoundries Inc.—have taken opposite approaches, leading them to have quite different design rules. Since there will not be easy portability between the two foundry groups, design teams may have to pick one track or the other.

There is also the still-unresolved lithography roadmap. Printers for critical layers at 16-nm might be EUV systems, or they might be massively-parallel e-beam direct-write systems. Or we might still be using 193-nm immersion lithography. Each choice requires different treatment of design data before the masks are made, and each would have different design rules.

"Despite all its problems, our bet is that we will still be using immersion at 193-nm," Sawicki said. "It will require us to use pixilated light sources and pixilated masks, with co-optimization between the source pattern, the mask shapes, and the design rules. And that will mean we will require about 20 teraFLOPS of computing power to prepare one mask layer in a reasonable time."

But what if none of that works? Sawicki said the industry is already seeing situations at around 25-nm where, after you guard-band for process variations—and especially for stress-related pattern dependence—the new node has less performance than the old one. Today, careful custom design in the cell libraries can stave off the problem. But that won’t work for ever. "When you can’t scale the process any more, then you start looking at 3-D—not as it’s used today, as a way to include dice from different processes, but what we call homogeneous 3-D, where you stack dice from the same process to increase density," Sawicki said.

But 3-D will have its own issues. We don’t fully understand, for instance, the impact of wafer thinning—necessary for 3-D devices through-silicon vias (TSVs)—on the transistors. Thinning may alter the stress on the transistor channels, altering the electrical characteristics of the device in perhaps unpredictable ways. Pattern dependence and especially the proximity to TSVs may amplify this effect. And, Sawicki warned, we may have to model the TSVs themselves as active devices instead of treating them like giant vias.

At 16-nm, free lunches will be few.