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Neon God
Question for anyone here. If we're heading for the ever more serious "dark ...
munggnum
It's interesting; some folks are having trouble seeing the forrest for the ...
Android processor shines light on dark silicon
Rick Merritt
8/24/2010 12:33 AM EDT
SAN JOSE, Calif. – Chip designers face a growing problem of dark silicon they cannot use due to rising power leakage. A new class of fine-grained, application-specific cores can help reclaim lost die area and create more efficient processors, said a University of California researcher developing a prototype Android processor that uses the approach.
"With each process node, the percent of a chip you can actively switch drops exponentially," said Nathan Goulding, a graduate student at UC San Diego in a paper at Hot Chips. "The utilization wall is here and scaling theory says it will just get worse," he said.
An experimental 45-nm block had 2.8 times less useable die area than a similar block in a 90nm part when handling the same function in a similar power envelop, he reported. The answer, Goulding said, is to create a variety of application-specific cores that could deliver eight- to eleven-fold energy savings compared to using a general-purpose CPU.
UCSD researchers are building the Green Droid application processor to prove out their concepts. They have already identified and designed--using their own automated tools--21 cores that handle energy intensive jobs specific to a Google Android handset.
The group's so-called Conservation cores run tasks that may consist of a handful of instructions or loops. They range from running some aspect of Android's Dalvik virtual machine to processing key code for Linux or memory management functions.
Goulding claims his team has put in 7mm2 of silicon the capability to run 43,000 fundamental instructions that cover 95 percent of the most energy intensive tasks of an Android handset. The cores are managed by a central MIPS processor, a CPU chosen simply because the university had access to the core.
One of the most interesting aspects of the project is the automated tool the group created to generate its cores. It consists of a compiler that condenses a group of instructions into a higher level task and a code generator that spits out the Verilog to run the job in silicon.
"We wanted to control the whole process of creating the cores," said Goulding.
The application-specific cores don't have the MIPS CPU's overhead of fetching general purpose instructions and managing low-level registers. However, much work remains.
The team has yet to determine how to keep a MIPS host in a low power state while the accelerator cores work and how to arbitrate access to shared memory. Although the Green Droid design is still in an early state, its concepts stirred plenty of questions at the conference.
"I haven’t seen anything in accelerator cores at this granularity before," said Marc Tremblay, a veteran processor designer who recently left the former Sun Microsystems for a position at Microsoft.
UCSD graduate student Nathan Goulding presents his concepts of application accelerators
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sols
8/24/2010 1:26 AM EDT
Amazing - come up with new fancy names for a few well known things and EETimes will write an article about you.
Relabel low activity factor to "dark silicon", hardware accelerators to "conservation cores" - and here it is.
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Dave.Dykstra
8/24/2010 2:20 AM EDT
sols comments are right to the point. However, it looks like the main issue here is to resolve the problem by somehow improving the areas that are utilized. I would more expect researchers at an esteemed institution such as UCSD to be looking for ways to make those "dark silicon" areas usable. At least they seem to have come up with a way to improve the situation, but that should not be the accepted norm.
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munggnum
8/24/2010 2:36 AM EDT
Sols sounds a bit jaded. I attended this talk, and it seemed reasonable to me. Dark Silicon was a term coined by ARM CTO Mike Muller back in 2009. The talk has some good data about where dark silicon is coming from and how bad it's going to get -- very bad. The technical idea is to use the dark silicon area to attack the problem that caused the dark silicon problem in the first place -- power. The "accelerators" that they propose seem different than conventional accelerators in that they are automatically generated and play nice with the memory system, and in that they are intended to reduce power consumption, not necessarily to increase performance. This is probably why they use the term conservation core as opposed to accelerator. In the article, there is some mention about issues with putting the MIPS core in a low power state while the accelerators are running, but that seems to me to be fairly easy to address through power-gating cells.
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sols
8/24/2010 3:01 AM EDT
I guess I have to explain basic design tradeoff: if performance is improved (or accelerated if you wish), then clock frequency and voltage can be dropped reducing energy/power. So acceleration/conservation are 2 sides of the same coin.
Regarding the novelty - there is already commercial tool at least several years in the market, which automatically generate ISA extensions or accelerators. Many technical papers were published on this topic, e.g.:
Automatic generation of application specific processors
International Conference on Compilers, Architecture and Synthesis for Embedded Systems, Pages: 137 - 147, 2003
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munggnum
8/24/2010 3:22 AM EDT
Sols, clearly you have some good insights, but the devil is in the details. Voltage scaling to save power is losing its effectiveness in current and future technologies because of threshold scaling limitations and insufficient Vdd overdrive. The AutoTIE work you mention, while very good, targets a much easier class of code, and does not report results on power reduction.
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Rick Merritt
8/24/2010 9:49 AM EDT
Indeed "dark silicon" and "utilization wall" are buzzwords. But the real juice here is that hardware accelerators are getting to the level of specific application workloads--and a group of college students can craft the design tools to generate them.
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garydpdx
8/24/2010 4:50 PM EDT
The innovation that I see is not in the homebrew design tools which carried out high level synthesis (HLS) but the idea of taking small pieces of Android OS middleware and accelerating each of them as small pieces of hardware. The small pieces add up, covering the available dark silicon (or some of what would have been dark).
Most C-to-hardware translation has focused on large pieces of C code (e.g., Impulse C) or compiled binaries (e.g., Binachip) to transform into a significant IP block on a FPGA or ASIC.
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Code Monkey
8/24/2010 4:40 PM EDT
This sounds a little like the sea-of-cores work Chuck Moore has been doing at GreenArrays. I didn't know about the "utilization wall" but it's another boost for async sea of cores, wierd as they are.
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KB3001
8/25/2010 2:41 PM EDT
As sols said, this kind of effort existed before, the real question for me is how generalisable is this work? I mean if you constrain yourself to a specific application, all sorts of optimisations are possible, but could the results of these optimisations e.g. application-specific cores, be harnessed for a wider range of applications, or is it a recurring investment we have to make? The key is to strike the right granularity, and produce a fully operational system. As the article states, work on coordinating the MIPS processor operations with the acceleration cores' (as well as the operations of these) has yet to be done. What would be the resulting overheads i.e. in terms of area, speed, power? The devil is indeed in the details.
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goafrit
8/25/2010 8:45 PM EDT
I seem to miss the innovation here. Are you telling me that this is new? For me, it is just the nomenclature that changed.
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martinm_de
8/28/2010 9:41 AM EDT
I guess dark silicon means a piece of circuitry which is powered off (disconnected from vdd) using a high threshold PMOS transistor to reduce the leakage current.
This exists for 10 years now.
Doing this on operating system level is very complicated - understandably - since operating systems do not have dedicated functions like FFT, Viterbi decoder , CDMA demodulator etc.
Operating systems probably need sorting, searching in lookup tables etc.
THe coding style of an OS would have to vary a lot when using hardware-based functions which have to be powered on a few clock cycles before they can be used:
instead of calling a function, you would have to
load data into a bufer, turn on the needed function, wait until it says 'I am ready' andthen fetch the result.
These functions, coded into hardware, should be
hardware independent like a good C library which is portable between different procesor sand different OSes.
Sounds like a logistic nightmare.
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munggnum
8/28/2010 12:16 PM EDT
It's interesting; some folks are having trouble seeing the forrest for the trees. UCSD is saying "mobile applications processors should be composed out of hundreds of specialized cores that can suck energy out of relatively small parts of the system but collectively attain 8x energy savings." Then they show how such a system would be constructed. They have reasonable solutions to many of the problems that have been listed above. This is definitely new.
For those who are actually interested in understanding the details, they can read the actual papers off of the authors' website:
http://greendroid.ucsd.edu/
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Neon God
8/28/2010 12:16 PM EDT
Question for anyone here. If we're heading for the ever more serious "dark silicon" challenges that munggnum speaks of, is that apt to be good for the leading semi IP developers (because it will lead to more ways for them to differentiate their product) or bad for them (because it will make the way forward grind to a halt as research starts bumping up against theoretical limits)?
I'm thinking, in particular, with regard to Ceva, the leader in DSP cores, though I'd be interested in anyone's thought as to the likely effects of the so-called "dark silicon" issue on the semi IP business as a whole.
Thanks in advance.
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