Huawei describes smart memory chip

PALO ALTO, Calif. – Networking giants are racing to create a new generation of smart memories to speed packet processing, creating smaller, faster line cards for their network routers and switches. Big system makers are working separately on competitive implementations which could someday be used broadly in their products.

Huawei Technologies discussed work on a first-generation smart memory that will pack 32 Mbytes of IBM embedded DRAM on a 45nm chip consuming 60W. It will include an array of packet processing elements to drive data rates at rates up to 100 Gbits/second and achieve at least 250 million memory accesses per second.

The device, which still requires some external DDR3 DRAM, is in a verification phase. Huawei plans to start work in a few months on a follow-on chip that could pack as much as 128 Mbytes eDRAM.

"Our ultimate goal is to replace all our memory using smart memory," said Sailesh Kumar, an engineer who presented a paper on the device at Hot Chips.

The smart memory chips could eliminate TCAMs and three of four network processors used on network line cards today. They will also replace large banks of standard DRAMs.

The smart memory chips are aimed at speeding as many as 16 different packet processing jobs that require a little bit of processing on great gobs of memory. Thus the first Huawei uses an array of memories linked to small packet processing blocks that include logic to handle atomic locking operations.

In Huawei's initial part, the array blocks are directly linked to share intermediate data. Final results are passed to an external DRAM and then to an external network processor.

"Once we add these logic blocks we can do a lot of work and significantly reduce I/O bandwidth requirements between a packet processing ASIC and a memory subsystem," said Kumar.

Huawei's Sailesh Kumar describes a 32 Mbyte eDRAM smart memory