Sematech completes 3-D chip pilot line

SAN JOSE, Calif. - In a step towards enabling true 3-D chips, Sematech announced the completion of its 300-mm, 3-D IC pilot line.

Operating at the College of Nanoscale Science and Engineering’s (CNSE) Albany NanoTech Complex in New York state, the pilot line is geared for 3-D chips based on through-silicon via (TSV) technology.

Sematech's pilot line includes all processes and test vehicles necessary to demonstrate the viability of the ''via-mid'' technology in conjunction with advanced CMOS.

Centered on 5-micron by 50-micron TSVs, the processes include TSV formation and metallization, wafer and die alignment, bonding, thinning, and the necessary metrology for these integration sequences.

“Our mission is to make 3-D through-silicon via (TSV) both manufacturable and affordable. We will prove its very real advantages over conventional, two-dimensional designs — especially in increased functionality and performance,” said Sitaram Arkalgud director of 3-D Interconnect at Sematech, in a statement.

Launched in 2005, Sematech's 3-D program was established to enable 300-mm equipment and process technology solutions for TSV manufacturing. During 2009, the program began to demonstrate 300-mm tooling, materials, and process module solutions necessary for 3-D TSV manufacturing for 300-mm wafers in 2012 and beyond.

Chip makers have been talking about this technology for a decade. Many see mass adoption for TSVs in 2012 or so. But to date, there are ''no significant quantities of 3D-TSV technology after 10 years'' in R&D, according to VLSI Research. ''High-volume TSV is still some years away.''

The global market for 3-D chips is forecast to reach $5.2 billion by the year 2015, according to Global Industry Analysts Inc.