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D. Desharnais
D. Desharnais
War of words erupts in rival PDK camps
Mark Lapedus
9/10/2010 12:04 AM EDT
SAN JOSE, Calif. – A war of words has broken out between Cadence Design Systems Inc. and a rival process design kit (PDK) group.
The Interoperable PDK Libraries (IPL) Alliance claims that Cadence is playing unfair, saying Cadence is issuing unfounded messages about IPL’s technology. Cadence dismisses the notion, saying its intentions are justified.
The IPL recently released its open standard for interoperable process design kits (iPDKs), which are supposed to reduce costs for analog and mixed-signal designs. It uses a p-cell library from Ciranova's PyCell Studio.
The technology competes against Cadence’s Virtuoso EDA tools. Cadence's p-cell libraries are written in a rival and proprietary language called Skill.
The problem is that when end-users call up an iPDK at a customer site, a warning message automatically pops up. It reads as follows: “WARNING* (DB-220704): The usage of non-SKILL Pcells in Virtuoso is not a supported feature.”
The IPL group claims the culprit is Cadence. The IPL group is demanding that Cadence take down and remove the message.
The IPL Alliance was started in 2007, with five founding members: AWR, Ciranova, SpringSoft, Silicon Navigator and Synopsys. Mentor Graphics and Pulsic joined as supporting members. The newest members are the following entities: TSMC, Helic, JEDAT, Magma, Micro Magic and Virage Logic. Recently, Altera, LFoundry, ST, TowerJazz and others joined the group.
Last month, Cadence declined to comment on the warning message. Recently, however, Cadence responded to the IPL group’s charges.
Steve Lewis, product marketing director at Cadence, said the warning message is justified. Cadence will support customers using its Virtuoso EDA tools, based on its Skill language, he said.
Some customers are using a mix-and-match strategy. In other words, some customers are using Virtuoso, but not Skill. Instead, some are using Virtuoso and Ciranova's PyCell Studio.
In that case, Cadence can’t stop customers from using the hybrid approach. But Cadence also warns customers that they are on their own and cannot guarantee the results.
Cadence will not offer support to customers in this case. “We don’t support PyCells,’’ Lewis said. ''We can’t guarantee the Virtuoso’s behavior with PyCells.’’
The same rational is used if a customer uses IPL’s technology. Cadence can’t stop a customer from using IPL’s iPDKs. But Cadence also wants to warn customers that it will not offer support to a customer using Virtuoso and PyCells.
In this case, Cadence is merely alerting customers with a warning message, he said. Lewis insisted that Skill-not PyCells-is optimized for Virtuoso. “We don’t think that PyCells is the right direction for a PDK,’’ he added.
Cadence, of course, is also protecting its huge installed base of Virtuoso EDA tools in the market. The IPL threatens Cadence’s custom EDA tools, which is why Cadence is playing unfair, according to the IPL.
Besides that, the IPL group claims that its technology based on PyCells is faster and superior than Skill in analog design. Jingwen Yuan, president of the IPL Alliance and strategic alliance manager at Synopsys, reiterated the group’s position and issued the following statement:
“IPL Alliance member companies and their customers using iPDKs have reported that Cadence Virtuoso issues a warning message indicating that non-SKILL PCells are not supported. The warning message started to appear when Virtuoso IC6.1.3 was first released. We believe this to be misleading. Our members and their customers have rigorously tested and validated that all iPDKs work in Cadence Virtuoso 6.x. The Python PCells (PyCells) in iPDK use the same OpenAccess PCell plug-in mechanism used by Cadence SKILL PCells and are completely interoperable. PyCells work correctly and yield the same results in Virtuoso, Custom Designer, Titan, and Laker.”
The Interoperable PDK Libraries (IPL) Alliance claims that Cadence is playing unfair, saying Cadence is issuing unfounded messages about IPL’s technology. Cadence dismisses the notion, saying its intentions are justified.
The IPL recently released its open standard for interoperable process design kits (iPDKs), which are supposed to reduce costs for analog and mixed-signal designs. It uses a p-cell library from Ciranova's PyCell Studio.
The technology competes against Cadence’s Virtuoso EDA tools. Cadence's p-cell libraries are written in a rival and proprietary language called Skill.
The problem is that when end-users call up an iPDK at a customer site, a warning message automatically pops up. It reads as follows: “WARNING* (DB-220704): The usage of non-SKILL Pcells in Virtuoso is not a supported feature.”
The IPL group claims the culprit is Cadence. The IPL group is demanding that Cadence take down and remove the message.
The IPL Alliance was started in 2007, with five founding members: AWR, Ciranova, SpringSoft, Silicon Navigator and Synopsys. Mentor Graphics and Pulsic joined as supporting members. The newest members are the following entities: TSMC, Helic, JEDAT, Magma, Micro Magic and Virage Logic. Recently, Altera, LFoundry, ST, TowerJazz and others joined the group.
Last month, Cadence declined to comment on the warning message. Recently, however, Cadence responded to the IPL group’s charges.
Steve Lewis, product marketing director at Cadence, said the warning message is justified. Cadence will support customers using its Virtuoso EDA tools, based on its Skill language, he said.
Some customers are using a mix-and-match strategy. In other words, some customers are using Virtuoso, but not Skill. Instead, some are using Virtuoso and Ciranova's PyCell Studio.
In that case, Cadence can’t stop customers from using the hybrid approach. But Cadence also warns customers that they are on their own and cannot guarantee the results.
Cadence will not offer support to customers in this case. “We don’t support PyCells,’’ Lewis said. ''We can’t guarantee the Virtuoso’s behavior with PyCells.’’
The same rational is used if a customer uses IPL’s technology. Cadence can’t stop a customer from using IPL’s iPDKs. But Cadence also wants to warn customers that it will not offer support to a customer using Virtuoso and PyCells.
In this case, Cadence is merely alerting customers with a warning message, he said. Lewis insisted that Skill-not PyCells-is optimized for Virtuoso. “We don’t think that PyCells is the right direction for a PDK,’’ he added.
Cadence, of course, is also protecting its huge installed base of Virtuoso EDA tools in the market. The IPL threatens Cadence’s custom EDA tools, which is why Cadence is playing unfair, according to the IPL.
Besides that, the IPL group claims that its technology based on PyCells is faster and superior than Skill in analog design. Jingwen Yuan, president of the IPL Alliance and strategic alliance manager at Synopsys, reiterated the group’s position and issued the following statement:
“IPL Alliance member companies and their customers using iPDKs have reported that Cadence Virtuoso issues a warning message indicating that non-SKILL PCells are not supported. The warning message started to appear when Virtuoso IC6.1.3 was first released. We believe this to be misleading. Our members and their customers have rigorously tested and validated that all iPDKs work in Cadence Virtuoso 6.x. The Python PCells (PyCells) in iPDK use the same OpenAccess PCell plug-in mechanism used by Cadence SKILL PCells and are completely interoperable. PyCells work correctly and yield the same results in Virtuoso, Custom Designer, Titan, and Laker.”
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mark.lapedus
9/10/2010 1:33 AM EDT
PDK war-Round 2! Who will win the battle?
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selinz
9/10/2010 4:22 PM EDT
This doesn't seem like Cadence is really doing anything unreasonable. It is likely that this was prompted by a customer demanding PyCells support. I believe that they would have served themselves better by not issuing the "warning."
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yalanand
9/11/2010 6:08 AM EDT
This is going to close battle. Though so many companies joined iPDK, some of the analog biggies like TI are shifting fully to Cadence by next year. Cadence is already feeling the competition heat and warning messages to the customers :).
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Daniel Payne
9/13/2010 4:05 PM EDT
Every EDA company has their own languages to extend and interact with tools:
Mentor: Ample, Tcl, Genie
Cadence: Skill, Tcl
Ciranova: Python
I truly hoped that Tcl/Tk would take over as a defacto standard, yet it didn't.
Because of the proliferation of languages it is reasonable to issue a warning message by Cadence when Python code is detected by Skill. A compromise may be to allow customers to simply suppress these messages with a switch setting.
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Daniel Payne
9/13/2010 7:16 PM EDT
I needed to update my comment because I just learned that TSMC has built, qualified and shipped these cells as part of their iPDK. This really isn't a language issue, it is more a marketing ploy by Cadence to cast Fear, Uncertainty and Doubt (FUD) upon users.
Virtuoso users have to simply pick up the phone and let Cadence know that this warning message needs to be removed.
Now let's get back to innovating our products instead of scaring EDA users.
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ESF
9/13/2010 6:30 PM EDT
I think “format battle” is incorrect. Fundamentally this is an IP issue between EDA vendors and IC companies. PDK’s are a form of IP. Design teams, and also foundries, simply need to decide who they want to control their PDK IP – themselves, or somebody else.
Besides, IP is supported by IP providers. We don’t see a parallel message, “Warning – the use of Synopsys Designware is not supported in EDA360.” You’d be forgiven for suspecting the difference relates to Virtuoso market power.
The trendy analogy is smartphones and apps, but a better one is VAX/VMS and Unix. Yes VAX/VMS was everywhere, but in the end, Unix customers got more done. Similarly, Cadence customers use PyCells not to abandon Virtuoso, but because PyCells help them get more done at sub-65nm geometries. PyCell and iPDK users get more from Virtuoso, not less. If that’s a bad thing for Cadence, then EDA really does need a new business model. If you were a Virtuoso competitor, you’d thank Cadence every day for that warning message.
The reality is that Custom IC design has outgrown any one company’s control; 28nm takes an ecosystem of foundries, EDA companies, IP providers, DFM specialists etc. That means open systems and interoperability. Cadence has served the industry richly in the past and still has much to contribute beyond, “non-Skill object detected.” This is a trend Cadence ought to be leading themselves, not ceding to others.
Eric Filseth
CEO, Ciranova
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D. Desharnais
9/14/2010 1:06 PM EDT
Because of character limitations, this comment is the first of 2 parts:
Multiple tens of thousands of customers use Virtuoso daily. These customers repeatedly tell us what matters most to them: stability in their full custom/analog design software and flows, that can span multiple process nodes, multiple projects, multiple geographies, and multiple design teams. Other vendors have a point of view that is understandable, but taking a customer-centric view, clearly customers need a dependable, production proven flow that drives the highest quality design with minimal risk.
When it comes to supporting customers for production design, it is critical that we can act quickly and comprehensively should a problem occur. This means having visibility into all aspects of the design and flow as needed in order to identify the root cause. Our ability to respond like this is a huge assurance to customers, and reflects our commitment to stand behind our products. It is important to note that TSMC’s iPDK does not equal PyCells. iPDK contains both full SKILL-based PCell support as well as Python-based PyCells. Thus Virtuoso users can use iPDK with unfettered success, and they do. Should a customer choose to use PyCells in their flow, we cannot and do not intend to prevent that, but as a means of full-disclosure, they need to understand the risks associated with the approach.
David Desharnais
Product Management, Cadence
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D. Desharnais
9/14/2010 1:06 PM EDT
Part 2 of 2:
We have based our warning alert due to actual experiences our customers have faced when trying to implement a hybrid approach as it was described in the original post. In a couple of serious cases now, a customer using PyCells in their design flow experienced unforeseen problems that resulted in schedule delays and non-deterministic results. Translation: non-forecasted delays and complications as back-and-forth ensued between all parties to determine root cause. Turns out root cause was not due to Cadence. In the end, this experience was not what the customer anticipated when they decided to try out a hybrid approach. As a result of cases like this we responded with our alert to help prevent these types of situations in the future.
At the end of the day, customers want to tape-out chips with predictability, the highest quality, on schedule, and with the least amount of hassle; and with a vendor that will stand behind them if and when the unexpected happens. We provide that level of service at Cadence, and using SKILL-based PCells with Virtuoso provides the most deterministic path to final design closure.
David Desharnais
Product Management, Cadence
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