Freescale DSP tackles scalable video coding

PORTLAND, Ore. -- Freescale Semiconductor's embedded DSP targets scalable video coding (SVC) using a customizable H.264/SVC algorithm for its StarCore DSP. The chip maker said its design enables cost-effective media gateways, high-end video conferencing systems and IPTV distribution systems by eliminating the need for Pentium-grade processors for coding.

"Today you need something like a fast Pentium processor to do SVC, making it both cost and power-consumption prohibitive for media gateways and the end points in most video conferencing systems," said John Dixon, media marketing manager at Freescale. "What we now offer with a DSP-based solution is a much lower price point for use with gateways, as well as the flexibility to scale down in the future to even smaller, less expensive DSPs-based devices."

SVC enables a single encoder to create a video streams that contains several sub-bitstreams that can be separately decoded by dropping packets, allowing algorithms to down-sample for lower spatial resolution, slower frame rates and lower quality--or a combination of the three--as required for specific viewing devices. Hence, it is said to solve problems with stutters and stops, choppy frames, delays, blurred motion and broken pictures suffered by traditional video conferencing systems.

The MSC825x DSP is the first to implement the H.264/SVC algorithm. It is touted a fully programmable part that can handle realtime 1080p video streams at 30 frames per second, but which can be down-sampled by clients to as slow as 176p at 7.5 frames per second. The StarCore-based DSP also encodes and decodes H.264/SVC, and handles over 30 other legacy voice and video compression algorithms.


Dixon claimed Freescale MSC825x is twice as fast as the Texas Instrument C64x. The MSC825x also comes with software migration tools for translating existing TI DSP code into Freescale DSP code, for one-, two-, four- or six-core processors.