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Tilera details 100-core processor
Dylan McGrath
9/27/2010 9:08 PM EDT
SAN JOSE, Calif.—Fabless chip vendor Tilera Corp. Monday (Sept. 27) detailed its third generation of multicore processors, headlined by an SoC that features 100 64-bit cores.
Presenting at the Linley Tech Processor Conference here, Bob Doud, director of marketing at Tilera, said the company's Tile-Gx product line would offer performance increases of two to eight fold compared to the company's current TilePro family. Doud said 16- and 36-core Tile-Gx devices would be sampling by the end of this year and that 64- and 100-core iterations of the family would begin sampling in mid-2011.
The 100-core Tile-Gx100, first announced by Tilera last October, will feature clock speeds of between 1 Ghz and 1.5 GHz, 32 megabytes of total cache and 546 gigabit per second peak memory. The chips are targeted toward an array of applications including cloud computing, digital video transcoding, wireless infrastructure and advanced networking.
As with previous Tilera products, the Tile-Gx devices will feature a mesh or "tile" 64-bit RISC processor architecture, which connects the cores through Tilera's proprietary iMesh on-chip network. Doud said the devices would support a broad range of high-speed interfaces, including XAUI, Double XAUi, SGMII, Interlaken, PCI Express and StreamIO. The devices will also feature several co-processing engines, including Tilera's proprietary Multicore iMesh Coprocessing Accelerator (MiCA).
Doud emphasized the advantage of Tilera's tile archticture, which emphasizes modular design aand power efficiency and is, according to Doud, highly scalable to a large number of cores. As chip vendors move forward with expanding the number of cores available on an SoC, the industry needs architectures that allow that scale so that it is not necessary to "reinvent the architecture for each new advance in core count," Doud said.
"There isn't really a limit to what you can do with this tile architecture," Doud said. "We think this is the way of the future."
Asked about similarities between its architecture and the mesh architecture developed years ago by researchers at the University of Texas-Austin, Doud said,
"What makes Tilera stand apart from research that has been done at UT Austin and Intel is that we are in commercial production with two generations of chips."
Later, Doud added, "We are seeing a lot of other companies embracing mesh. We encourage that. We think that mesh is the way to go in the future. We just have a little bit of a lead."
Earlier at the conference, Linley Gwennap, principal analyst at the Linley Group, said revenue from dual-core and multicore processors will account for only about 25 percent of networking and communications chip revenue in 2010. Noting that the long development cycle means that design wins take three to five years to translate into revenue, Gwennap said revenue from dual-core networking and communications chips is projected to surpass single-core revenue in 2013.
Presenting at the Linley Tech Processor Conference here, Bob Doud, director of marketing at Tilera, said the company's Tile-Gx product line would offer performance increases of two to eight fold compared to the company's current TilePro family. Doud said 16- and 36-core Tile-Gx devices would be sampling by the end of this year and that 64- and 100-core iterations of the family would begin sampling in mid-2011.
The 100-core Tile-Gx100, first announced by Tilera last October, will feature clock speeds of between 1 Ghz and 1.5 GHz, 32 megabytes of total cache and 546 gigabit per second peak memory. The chips are targeted toward an array of applications including cloud computing, digital video transcoding, wireless infrastructure and advanced networking.
As with previous Tilera products, the Tile-Gx devices will feature a mesh or "tile" 64-bit RISC processor architecture, which connects the cores through Tilera's proprietary iMesh on-chip network. Doud said the devices would support a broad range of high-speed interfaces, including XAUI, Double XAUi, SGMII, Interlaken, PCI Express and StreamIO. The devices will also feature several co-processing engines, including Tilera's proprietary Multicore iMesh Coprocessing Accelerator (MiCA).
Graphical depiction of Tilera's tile architecture, which the company says is power efficienthighly scalable. Source: Tilera Corp.
Doud emphasized the advantage of Tilera's tile archticture, which emphasizes modular design aand power efficiency and is, according to Doud, highly scalable to a large number of cores. As chip vendors move forward with expanding the number of cores available on an SoC, the industry needs architectures that allow that scale so that it is not necessary to "reinvent the architecture for each new advance in core count," Doud said.
"There isn't really a limit to what you can do with this tile architecture," Doud said. "We think this is the way of the future."
Asked about similarities between its architecture and the mesh architecture developed years ago by researchers at the University of Texas-Austin, Doud said,
"What makes Tilera stand apart from research that has been done at UT Austin and Intel is that we are in commercial production with two generations of chips."
Later, Doud added, "We are seeing a lot of other companies embracing mesh. We encourage that. We think that mesh is the way to go in the future. We just have a little bit of a lead."
Earlier at the conference, Linley Gwennap, principal analyst at the Linley Group, said revenue from dual-core and multicore processors will account for only about 25 percent of networking and communications chip revenue in 2010. Noting that the long development cycle means that design wins take three to five years to translate into revenue, Gwennap said revenue from dual-core networking and communications chips is projected to surpass single-core revenue in 2013.
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Dr DSP
9/27/2010 11:47 PM EDT
Any way to remove these SPAM comments? How about adding a report SPAM button next to Follow Comments?
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phoenixdave
9/27/2010 11:53 PM EDT
The SPAM comments have been around almost nightly for some time, and I know that they are working to resolve them. They are certainly annoying...
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http://www.lulu.com/spotlight/poconoarmchairreview
9/28/2010 12:37 AM EDT
Wish I had one of these 100-core processors to play around with. I'd love to see what it can do with one of my neural net simulations.
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rdeva
9/28/2010 11:03 AM EDT
impressive. 100 64-bit cores with 546 gbps b/w.. thats one hell of a processing node.
PS.
by any chance, its a designer typo for quadcore??
(0x100 = 4) :P
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rdeva
9/28/2010 11:04 AM EDT
*0b00 = 4
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Warren
9/28/2010 12:39 PM EDT
wish there was an "undo" or "delete" button rdeva? :)
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BobsUrUncle
9/28/2010 2:46 PM EDT
Interesting. But seen these types of anouncements come and go. It's got to be a nightmare to debug code in this chip.
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selinz
9/28/2010 3:38 PM EDT
It would be nice if some speculation on which applications would benefit from 100 cores... It seems excessive..
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eewiz
9/29/2010 2:59 AM EDT
I think huge datacentres/Cloud servers can benefit from this CPU. They can now compress 10-20 racks to a single one with this CPU. Also power/performance ratio might be better than the normal x86 servers.
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TileGuy
9/29/2010 11:27 AM EDT
Yes, cloud & other datacenter apps are right in our crosshairs. Also there are tons of embedded applications ranging from 40Gbps+ "deep packet touch" applications (IPS, data mining), to multimedia applications like audio/video transcoding (think YouTube video sent to your iPhone), broadcast video infrastructure like Video-on-Demand, and so on.
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prabhakar_deosthali
9/29/2010 1:57 AM EDT
Such huge multi-core SOCs need to be supported by equally powerful Software development tools . The simulation of an application using such an SOC will need very powerful workstations or a cluster of workstations with the same network topology and speeds as in the target SOC. Is the company providing such tool sets?
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TileGuy
9/29/2010 11:21 AM EDT
Good point! Yes, Tilera has invested a huge amount in SW tools and we also are leveraging standards-based tools such as gdb and gprof. We've enhanced many open source tools to make them multicore friendly with graphical UI's that let you see what's happening on each tile. Check out our Website.
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sqdk
9/29/2010 6:51 PM EDT
Nice design.
Has Tilera any plans for PCIe based eval boards ?
Seems well suited for properly designed multi-core, multi-threaded software.
Most open source and close source software is not well suited or explicit written for this level of multiprocessing, it requires a major redesign/rewrite of the debugging and tracing tools to handle parallel programming issues properly for large scale projects.
Can You detail the 546 Gbit memory peak bandwidth ? Could be a limiting factor for keeping 100 64bit cores fully loaded for parallel streamprocessing tasks.
Are all the cores able to load 64bit non-blocking ?
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