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R_Colin_Johnson
For a direct bandgap material, like III-V, an electron near the bottom of the ...
R_Colin_Johnson
That, of course, is one of the issues that IBM engineers are working on as we ...
IBM debuts CMOS silicon nanophotonics
R Colin Johnson
11/30/2010 8:01 PM EST
PORTLAND, Ore.—Silicon chips will be communicating with pulses of light instead of electrical charge starting in 2011, according to International Business Machines Corp., which described its CMOS Integrated Silicon Nanophotonics (CISN) technology Wednesday (Dec. 1) at a tradeshow.
At Semicon Japan in Chiba, Japan, IBM (Armonk, N.Y.) heralded silicon nanophotonics as the enabler for future exascale processors that can execute a million trillion operations per second (1,000-times faster than today's petascale supercomputers).
"The CMOS silicon nanophotonics technology we have developed at IBM can meet the requirements for exascale systems, by scaling up per-chip transceiver bandwidth and integration density," said Will Green, an IBM researcher involved with the CISN project. Green worked on CISN with Yurii Vlasov, manager of silicon integrated nanophotonics at its T.J Watson Research Center in Yorktown Heights, N.Y., and fellow researchers Solomon Assefa, Alexander Rylakov, Clint Schow and Folkert Horst.
For nearly a decade, IBM, Hewlett-Packard Co., Intel Corp., Freescale Semiconductor Inc., NEC Electronics Corp., Samsung Electronics Co. Ltd., IMEC and dozens of their partners—from Avago Technologies Ltd. to Luxtera Inc.—have promised silicon photonics as the inevitable future of CMOS. By integrating electrical-to-optical and optical-to-electrical transceivers onto traditional CMOS chips, silicon photonics promises to break the bottleneck now holding back development of exascale computing platforms. IBM now claims to have solved this problem with its CISN technology which is currently being licensing to partners, and which will begin to appear in commercial transceivers starting in 2011.
"The situation is similar to when Marconi demonstrated the first transatlantic radio transmission," said Rick Doherty, principal analyst at The Envisioneering Group (Seaford, N.Y.). "Today there are oceans separating our digital systems, boards and chips, but now IBM has proven that optical interconnects can crossover those oceans using traditional, integrated CMOS lithography."
Since 2005, IBM Research has been assembling the silicon photonic components needed to create the entire ecosystem of CMOS optical connectivity required to enable electronic chips to communicate with light over optical interconnects instead of copper traces and busses. So far, IBM has demonstrated optical modulators, wave guides, wavelength-division multiplexers, switches and detectors—all cast in CMOS. The remaining component—a silicon emitter—was also demonstrated at IBM by adding a nanotube, but IBM's integrated silicon photonics due out next year will instead use a traditional III-V emitter.
One major stumbling block recently removed by IBM for its CISN technology was the ability to bury a germanium layer at the bottom of its CMOS stack. Others like Freescale, working with startup Luxtera, have demonstrated silicon optical transceivers using that use a germanium-last process, but IBM claims its germanium-first process enables a 10-to-1 reduction in die size, enabling 65-nanometer CMOS chips to house silicon optical transceivers in just a half a square millimeter (which can be ganged together for terabit-per-second speeds in less than five-by-five millimeters).
IBM is currently characterizing the manufacturability of its CISN process in commercial foundries, and predicts that the first availability of CMOS optical transceivers from its licensees will begin next year. IBM predicts that its CISN will then work its way from connecting systems to connecting boards in the same system, to connecting chips on the same board, to eventually connecting cores on the same CMOS microprocessor by 2016.
At Semicon Japan in Chiba, Japan, IBM (Armonk, N.Y.) heralded silicon nanophotonics as the enabler for future exascale processors that can execute a million trillion operations per second (1,000-times faster than today's petascale supercomputers).
"The CMOS silicon nanophotonics technology we have developed at IBM can meet the requirements for exascale systems, by scaling up per-chip transceiver bandwidth and integration density," said Will Green, an IBM researcher involved with the CISN project. Green worked on CISN with Yurii Vlasov, manager of silicon integrated nanophotonics at its T.J Watson Research Center in Yorktown Heights, N.Y., and fellow researchers Solomon Assefa, Alexander Rylakov, Clint Schow and Folkert Horst.
For nearly a decade, IBM, Hewlett-Packard Co., Intel Corp., Freescale Semiconductor Inc., NEC Electronics Corp., Samsung Electronics Co. Ltd., IMEC and dozens of their partners—from Avago Technologies Ltd. to Luxtera Inc.—have promised silicon photonics as the inevitable future of CMOS. By integrating electrical-to-optical and optical-to-electrical transceivers onto traditional CMOS chips, silicon photonics promises to break the bottleneck now holding back development of exascale computing platforms. IBM now claims to have solved this problem with its CISN technology which is currently being licensing to partners, and which will begin to appear in commercial transceivers starting in 2011.
"The situation is similar to when Marconi demonstrated the first transatlantic radio transmission," said Rick Doherty, principal analyst at The Envisioneering Group (Seaford, N.Y.). "Today there are oceans separating our digital systems, boards and chips, but now IBM has proven that optical interconnects can crossover those oceans using traditional, integrated CMOS lithography."
IBM's all silicon optical transceivers house modulators, wave guides, wavelength-division multiplexers, switches and detectors all cast the same CMOS die.
Since 2005, IBM Research has been assembling the silicon photonic components needed to create the entire ecosystem of CMOS optical connectivity required to enable electronic chips to communicate with light over optical interconnects instead of copper traces and busses. So far, IBM has demonstrated optical modulators, wave guides, wavelength-division multiplexers, switches and detectors—all cast in CMOS. The remaining component—a silicon emitter—was also demonstrated at IBM by adding a nanotube, but IBM's integrated silicon photonics due out next year will instead use a traditional III-V emitter.
One major stumbling block recently removed by IBM for its CISN technology was the ability to bury a germanium layer at the bottom of its CMOS stack. Others like Freescale, working with startup Luxtera, have demonstrated silicon optical transceivers using that use a germanium-last process, but IBM claims its germanium-first process enables a 10-to-1 reduction in die size, enabling 65-nanometer CMOS chips to house silicon optical transceivers in just a half a square millimeter (which can be ganged together for terabit-per-second speeds in less than five-by-five millimeters).
IBM is currently characterizing the manufacturability of its CISN process in commercial foundries, and predicts that the first availability of CMOS optical transceivers from its licensees will begin next year. IBM predicts that its CISN will then work its way from connecting systems to connecting boards in the same system, to connecting chips on the same board, to eventually connecting cores on the same CMOS microprocessor by 2016.
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R_Colin_Johnson
12/1/2010 2:19 AM EST
In 2011, IBM will debut Blue Waters which it described in Tokyo Dec. 1st. Blue Waters will not only be the world's fastest supercomputer, but will feature a Terabit-per-second optical interconnect using Avago's microPOD. IBM did not announce any licensees to its CMOS Integrated Silicon Nanophotonics in Tokyo, but analysts told me that its CISN will likely be licensed to others for manufacturing as early as next year. One analyst suggested that a big manufacturer like Samsung might license CISN if it becomes convinced that optical interconnects have, after many years of speculation, finally arrived.
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iniewski
12/1/2010 10:52 AM EST
But there is still no silicon emitter in IBM technology! Adding III-V laser on a CMOS chip is not a cheap option! Kris
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R_Colin_Johnson
12/10/2010 6:45 PM EST
IBM has a silicon emitter, but it is a hybrid that uses a carbon nanotube: htp://bit.ly/eHrLjj
However when I asked IBM about it, they said cost-wise no silicon emitter could yet compete with III-V emitters in performance or cost, and until they do no one should switch.
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greenpattern
12/1/2010 4:23 PM EST
These waveguides being half-wavelength limited, they can't allow for high density in the infrared. So the WDM is supposed to help but this still translates into different allocated source/receiver areas for different wavelengths, if I understand it correctly.
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sranje
12/1/2010 4:53 PM EST
These must be SOI wafers - one of IBM's strengths in advanced nodes. How exciting !!
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iniewski
12/1/2010 7:00 PM EST
Yes, this is SOI for sure...losses in bulk silicon would be too large...exciting yes, practical dunno...Kris
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agk
12/3/2010 3:30 AM EST
Nano photonics processors are so fast and new artificial intelligence machines will be possible.Many types of algorithms can go in to it and the speed is the advantage for computing.Hope soon multi core processors and FPGA technology will be out dated!!!
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goafrit
12/3/2010 5:39 AM EST
I thought Intel came up with this last year. The whole region of optical interconnect. Maybe the IBM is doing it at the domain of nano systems.
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R_Colin_Johnson
12/10/2010 6:52 PM EST
Intel has many of the components for silicon photonics, including a hybrid emitter that uses a III-V flake, but IBM claims it is the only vendor that has downsized its photonic components enough to make them commercially feasible.
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iniewski
12/3/2010 10:13 AM EST
to @agk, not so fast, photonics can be very fast for data transfer (as in the article) but is usually terrible for computation...so the best case is CMOS for computation and photonics for interconnects (only some interconnects of course, local interconnects will be still copper)...realistically you might be able to make a few supercomputers this way but general use is several years away, if that...Kris
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iniewski
12/8/2010 2:56 PM EST
To @new2coding: silicon on nothing (SON) has been actually proposed several years ago in Europe and has been patented...Kris
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iniewski
12/8/2010 4:30 PM EST
@newcoding, yes, that is 2004 IEEE paper that STM has published, they own some patents in this area...you are right this covers the MOSFET, not sure about the whole IC etc...Kris
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iniewski
12/10/2010 6:50 PM EST
Thank you Colin. Yes, silicon emitter would have poor performance, carbon nanotube based or else (BTW, carbon nanotube laser sounds like a long shot)...and III-V laser would be lower cost, but only if manufactured in III-V process...I think it will be very expensive if manufactured in silicon process, imagine how many process steps will be require to add that laser, enormous complexity, hardly a manufacturable solution! Kris
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R_Colin_Johnson
12/12/2010 2:31 PM EST
Yes, Intel has successfully grafted a flake of III-V onto a silicon chip as an emitter, but not in a production environment. I believe that instead of fabricating III-V materials on CMOS chips, that instead IBM is figuring on using a traditional discrete III-V emitter and just piping its emissions onto its CISN chips with fiber optics, where the silicon modulators will take over translating electrical data into optical data.
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iniewski
12/10/2010 7:12 PM EST
No, silicon has indirect bandgap, that is the whole problem...you really have to twist its bonds to produce coherent light...regardless of the wavelength...Kris
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iniewski
12/13/2010 10:38 AM EST
thank you Colin...this approach seems to be much more practical...but clearly some issues remain, how do you synchronize off chip III-V laser signals with some on chip CMOS generated signals? Kris
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R_Colin_Johnson
12/13/2010 11:49 AM EST
That, of course, is one of the issues that IBM engineers are working on as we speak. And you can bet IBM is also working on process/material/archtectural innovations to overcome the hurdles to silicon emitters.
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