Samsung tips six predictions in IC scaling
12/6/2010 2:49 PM EST
SAN FRANCISCO - As IC technology enters the sub-20-nm era, chip scaling will become even more difficult and expensive, thereby possibly requiring new materials, structures and processes, according to a technologist from Samsung Electronics Co. Ltd.
During a keynote at the International Electron Device Meeting (IEDM) here, Kinam Kim, president of Samsung Advanced Institute of Technology, said that the cost of IC scaling could force the industry to migrate to 3-D devices, based on through-silicon via (TSV) technology.
Memory technology will scale to the 1x-nm node, but the industry must also look at a new class of products that could replace existing DRAM and NAND, such as MRAM, phase-change and ReRAM, Kim said.
''The current 30-nm node silicon technology is meeting the demand for extremely low power, multifunctional chips that are able to maintain high performance to process and store huge amounts of heterogeneous data,’’ Kim said. ‘’However, there are concerns on whether the current silicon technology can satisfy the technical requirements and overcome the ultimate limits attached to transistors scale down.’’
Here’s some of Kim’s predictions and the associated challenges, which were presented during the keynote:
1. Logic scaling
''At gate lengths less than 20 nm, the use of conventional planar transistors will be nearly impossible because of the extremely thin gate dielectric and junction depths,’’ Kim said.
''Fortunately, silicon technology can be extended thanks to fully depleted (FD) devices such as FD-SOI and multi-gate (MuG) FinFETs. FD device technology is being transferred from R&D to manufacturing. It is expected that the EOT of MuG devices would follow the same trend as the historical SiON EOT trend.
2. TSV-based 3-D parts
Scaling is becoming expensive, causing chip makers to look at TSV-based devices. ''Many groups have reported through-silicon-via based 3D IC (TSV-3D IC) where a single integrated circuit is built by stacking silicon wafers or dies and interconnecting them vertically so that they behave as a single device,’’ Kim said.
''There are many challenging processes such as TSV sidewall etch profiles, poor isolation liners and barrier profiles. These can cause TSV reliability issues due to copper diffusion into the bulk material. In addition to process challenges, there are chip design related issues that need to be resolved in order to maximize the advantage of the TSV-3D IC technology. These issues are: 3D floor-planning (TSV size, the proximity of TSVs to neighboring transistors, and routing with TSVs), thermal management, coefficient of thermal expansion (CTE) mismatch between Cu and Si and mechanical stability,’’ he said.
3. DRAM scaling
Right now, Samsung believes it can scale the DRAM down to at least the 1x-nm node. According to Samsung’s roadmap, the company is currently shipping DRAMs based on 35-nm technology. Samsung plans to ship DRAMs based on 2x-nm technology in 2013 and hopes to devise a 1x-nm part by 2016.
''The most crucial element required for continuing the migration from 30-nm through 20-nm and to ultimately sub-10 nm are: patterning capability of lithography, technological breakthroughs of cell capacitors and transistors from both process and device points of view,’’ Kim said.
''DRAM cell capacitors are most challenging due to its stringent process requirements. The sensed signal should be larger than the noise to guarantee successful sensing. Cell capacitance must be maintained higher than around 20fF per cell, regardless of the technology node,’’ he said.
4. NAND scaling
Like DRAMs, Samsung believes NAND flash will continue to scale at least until the high 1x-nm node.
''NAND flash cell architecture based on the floating gate concept has not changed much since its conception. At each design node, barriers have been overcome by introducing breakthrough process technologies (patterning and dielectric/metal layers) and circuit innovations such as error-correction code (ECC), parallel/shadow programming, wear-level management, data compression schemes, etc.,’’ Kim said.
''However, short-channel-effects (SCE) and decreased number of stored electrons will impede further scaling of planar NAND flash technology at around the 10 nm node,’’ he said.
5. 3-D NAND
Beyond NAND, Micron, Samsung and Toshiba propose to devise 3-D NAND, in which vendors stack parts in a 3-D structure.
''Out of the proposed 3D NAND structures, tera-bit CAT (TCAT) structure is the most promising because it enables the use of a TANOS (CTF with high work function gate and high-k blocking oxide) scheme. Erase speeds can be improved with a high work function gate and tunnel barrier engineering. Retention time can be greatly improved by optimizing blocking layers with combined structures of high-k dielectric oxide,’’ Kim said.
6. Universal memory choices
3-D NAND could be expensive and difficult to make. Other technologies, including so-called universal memories, are in the works. FeRAM, MRAM, phase-change and ReRAM are leading candidates.
''Process issues of 3D NAND have led to consider other numerous schemes for sub-10 nm nodes. According to results of an ITRS poll about the next nonvolatile memories, crossbar type resistive random access memory (ReRAM) ranked top as a strong candidate for the 16 nm and beyond nodes. ReRAM has the advantage of using a simple cross bar structure that can be easily stacked,’’ Kim said.
''PRAM and spin torque transfer (STT) MRAM are other storage class memory candidates. PRAM is now being adopted in mobile phone applications as a code storage memory. The advantage of PRAM is that it can be scaled down to the 15 nm node and beyond. In STT MRAM, much progress on the switching current reduction, circuit, and architecture have been achieved,’’ he said.