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Or_Bach
Now that we have change our name to MonolithIC 3D Inc. we have update our web ...
Or_Bach
Now that we have change our name to MonolithIC 3D Inc. we have update our web ...
Startup outlines monolithic 3-D chips
R Colin Johnson
12/9/2010 11:05 PM EST
PORTLAND, Ore.—True monolithic three-dimensional (3-D) silicon chips will beat die stacked with through-silicon-vias (TSVs) by a factor of 10,000 in connectivity, according to serial entrepreneur Zvi Or-Bach, founder of NuFGA Inc. and a past winner of the EE Times Innovator of the Year Award. Or-Bach will show how to make true monolithic 3-D chips at the 3-D Architectures for Semiconductor Integration and Packaging conference in Burlingame, Calif.
"We have been able to make significant progress in monolithic 3-D, and now have the intellectual property (IP) in place for two methods," said Or-Bach, who pioneered ASICs at eASIC and later at Chip Express and is now president and CEO of startup NuPGA (San Jose, Calif.).
According to Or-Bach, NuPGA's 3-D IC fabrication techniques can be used to stack memory on top of a processor, to stack bit-wide memory chips into byte-wide configurations or just to shrink the die of existing designs by optimizing chip area versus height. Any number of chip layers can be composed, according to Or-Bach, enabling general-purpose monolithic 3-D to reduce chip areas by as much as three times over conventional 2-D.
"Others like BeSang have found ways to put vertical transistors on top of logic, for instance as memory cells, but we have discovered a two ways to make horizontal transistors, which can be used for almost anything," said Or-Bach.
The main problem with going 3-D is that the temperatures required to create conventional silicon transistors on the top layer—up to 900 degrees Celsius—will melt the already formed transistors on the lower layers. NuPGA's technique sidesteps that issue by bonding a top wafer that has already had its high-temperature processing done, leaving only low-temperature etching and metallization to finish the 3-D design.
Both techniques start with a finished CMOS chip for the bottom layer, which is then covered with an insulating oxide and bonded to the donar wafer. In the first technique, a donar wafer is fabricated into a single giant transistor. After bonding, the giant transistor can be etched into individual transistors which are then interconnected with metallization.
To create 3-D chip layers with both n-type and p-type transistors, the donar chip must already be fabricated with dummy gates, which can be etched and interconnected after wafer bonding.
NuPGA's second technique fabricates a sea of transistors on the donar wafer, but each with a dummy placeholder for its gates. After a novel bonding step, which aligns the chips with an effective accuracy of 100 nanometers, the top layer transistors are finished by etching out the dummy gates and adding the top metallization layer.
NuPGA hopes to license its techniques, which have yet to be proven out with 3-D prototype chips, to existing semiconductor makers.
"We have been able to make significant progress in monolithic 3-D, and now have the intellectual property (IP) in place for two methods," said Or-Bach, who pioneered ASICs at eASIC and later at Chip Express and is now president and CEO of startup NuPGA (San Jose, Calif.).
According to Or-Bach, NuPGA's 3-D IC fabrication techniques can be used to stack memory on top of a processor, to stack bit-wide memory chips into byte-wide configurations or just to shrink the die of existing designs by optimizing chip area versus height. Any number of chip layers can be composed, according to Or-Bach, enabling general-purpose monolithic 3-D to reduce chip areas by as much as three times over conventional 2-D.
"Others like BeSang have found ways to put vertical transistors on top of logic, for instance as memory cells, but we have discovered a two ways to make horizontal transistors, which can be used for almost anything," said Or-Bach.
The simplest way to create 3-D chips is to fabricate
the bottom chip as usual, cover it with oxide, then bond it to a
similarly oxide clad giant-transistor donar chip, which can then be
etched into individual transistors.
The main problem with going 3-D is that the temperatures required to create conventional silicon transistors on the top layer—up to 900 degrees Celsius—will melt the already formed transistors on the lower layers. NuPGA's technique sidesteps that issue by bonding a top wafer that has already had its high-temperature processing done, leaving only low-temperature etching and metallization to finish the 3-D design.
Both techniques start with a finished CMOS chip for the bottom layer, which is then covered with an insulating oxide and bonded to the donar wafer. In the first technique, a donar wafer is fabricated into a single giant transistor. After bonding, the giant transistor can be etched into individual transistors which are then interconnected with metallization.
To create 3-D chip layers with both n-type and p-type transistors, the donar chip must already be fabricated with dummy gates, which can be etched and interconnected after wafer bonding.
NuPGA's second technique fabricates a sea of transistors on the donar wafer, but each with a dummy placeholder for its gates. After a novel bonding step, which aligns the chips with an effective accuracy of 100 nanometers, the top layer transistors are finished by etching out the dummy gates and adding the top metallization layer.
NuPGA hopes to license its techniques, which have yet to be proven out with 3-D prototype chips, to existing semiconductor makers.
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kdboyce
12/10/2010 1:43 AM EST
See my other comments at:
http://www.eetimes.com/electronics-news/4211391/3-D-chips-moving-out-of--PowerPoint--era-
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3D Guy
12/10/2010 10:03 AM EST
Interesting article. The key point with this technology seems to be the use of manufacturing-friendly transistors such as RCATs that have been used in DRAM production (can see RCATs shown in figures above). Will make adoption easier.
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R_Colin_Johnson
12/10/2010 12:54 PM EST
Yes, Or-Bach will speak about NuPGA's use of RCATs and a lot more about how true monolithic 3D could solve today's interconnection problems and also cut the heat they generate. He will also present his case for the many advantages of true monolithic 3D that I didn't mention, such as that each stacked chip is only 50-100 nanometers thick, compared to TSV stacked chips which are 50 microns thick, thus permitting many more chip layers to be stacked up using true monolithic 3D.
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pixies
12/10/2010 3:40 PM EST
Well, if the layers are stacked 1,000 times closer, the heat, which already is a huge problem for stacked chip approach, will be even more of a headache.
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R_Colin_Johnson
12/10/2010 6:37 PM EST
Yes, heat is a problem that is not going away--ever, according to Or-Bach, who claims its solution is the same as it always was. He claims that no new heat-sinking methods are needed, but rather that designers just have to learn how to manage heat in 3D!
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3D Guy
12/10/2010 10:13 PM EST
The biggest markets for semiconductors 5-10 years from now will be portable electronic devices like cell phones, smart phones and tablet computers. Logic chips used for these markets burn very little power and in fact are 3D stacked today with wire-bonding to save space. Heat removal is far less of an issue with these low power chips. I predict that 3D will take off in a big way due to these huge markets and their lower susceptibility to heat removal issues.
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TravisOR
12/10/2010 7:28 PM EST
Reduction of heat dissipation issue in TRUE 3D IC comes from product architecture which places slow functional blocks, such as memory cell array, on top and high speed logic including sense amplifier on the bottom substrate. This product architecture architecture scheme cannot be implemented with TSV because each memory cells on top should be accurately aligned to bottom logic within few nanometer misalignment. More information is available at http://www.besang.com. Check the video interview with Junil Park, VP of Technology at BeSang Inc.
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R_Colin_Johnson
12/12/2010 2:17 PM EST
Anybody who is interested in the perils and progress in true monolithic 3D should check with BeSang, which has been working on these tough engineering tasks for several years now.
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TravisOR
12/10/2010 7:43 PM EST
If we consider one time read/write all cells of 1 Gb memory, then, most cells operates twice only while some logic runs billion times. Power consumption is proportional to frequency. Therefore, logic should be placed on silicon substrate for fast heat dissipation through bottom substrate. Memory cell on top of 3D IC will be fine even though dielectric layers have poor heat conduction because memory cells in general do not generate heat problem.
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3D Guy
12/10/2010 10:12 PM EST
The biggest markets for semiconductors 5-10 years from now will be portable electronic devices like cell phones, smart phones and tablet computers. Logic chips used for these markets burn very little power and in fact are 3D stacked today with wire-bonding to save space. Heat removal is far less of an issue with these low power chips. I predict that 3D will take off in a big way due to these huge markets and their lower susceptibility to heat removal issues.
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nicolas.mokhoff
12/11/2010 12:36 PM EST
kdboyce: I could not agree more. It's a far cry from paper designs and simulations to practice runs. Wishing Or-Bach the best with his ideas turning into products. But the only way to so is to present the original idea in forums like this to get others to think "outside the box".
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hm
12/12/2010 11:06 PM EST
This may have vast application in sapce and defence industry. For them conserving space is very crucial. How about the reliability aspect of these monolithic 3D devices? Will they have new qualification procedure for space application? Also, what will be implications on required EDA design tools?
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R_Colin_Johnson
12/13/2010 12:08 AM EST
Not sure, but I would think the EDA tools won't need too much of a tweak, since they already deal with multiple layers--just more of them for 3D ICs.
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chrisaliin
12/13/2010 1:20 AM EST
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Bob Lacovara
12/13/2010 9:56 AM EST
Paraphrasing from "Apocalypse Now", "Oh, the Heat". I'm sure that rational arrangements of layers with respect to the base will help, but heck, the whole point is to cram as much heat-generating circuitry into the smallest area possible. Perhaps it's time to start running coolant through the 3D array? Or shape the 3D arrays as other than apartment houses?
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R_Colin_Johnson
12/13/2010 12:16 PM EST
The a pipe-dream "cool" solution would be to sandwich a thermo-electric material between layers that converts the heat into electricity that cuts power too!
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elctrnx_lyf
12/13/2010 12:36 PM EST
The 3D chip technology is shaping up very fast and I hope the industry could reap the benefits of this technology in the recent future. To see the semiconductor technology to grow as Moore told, there is necessity of such technologies. What are all the products that could really reap the benefits of this technology?
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Or_Bach
4/1/2011 4:32 AM EDT
Now that we have change our name to MonolithIC 3D Inc. we have update our web site and put a lot of interesting information including a very active blog http://www.monolithic3d.com/blog.html. I highly recommend going through it as many of the issues discussed above a re covered in details there.
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Or_Bach
4/1/2011 4:30 AM EDT
Now that we have change our name to MonolithIC 3D Inc. we have update our web site and put a lot of interesting information including a very active blog http://www.monolithic3d.com/blog.html. I highly recommend going through it as many of the issues discussed above a re covered in details there.
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Or_Bach
4/1/2011 4:31 AM EDT
Now that we have change our name to MonolithIC 3D Inc. we have update our web site and put a lot of interesting information including a very active blog http://www.monolithic3d.com/blog.html. I highly recommend going through it as many of the issues discussed above a re covered in details there.
Sign in to Reply