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Simonstar
It is an exciting time to be in the semiconductor industry because you get to ...
iniewski
Interesting blog @Or_Bach, perhaps you can get Zvi or Deepak to give a talk at ...
Moore's Law could enter the fourth dimension--via the third
Zvi Or-Bach
12/23/2010 12:43 AM EST
I was intrigued by Marvell CEO Sehat Sutardja's call in EE Times to "change and rethink Moore's Law to include the long-ignored fourth dimension" of power consumption efficiency. "What we need now is a new social contract," Sutardja wrote.
Calling Moore's Law a social contract is one way to look at it. Others see it as a self-fulfilling prophecy, or at least it has been so for the past 45 years. Ray Kurzweil claims it is a part of the Law of Accelerating Returns, whereby computing devices have been consistently multiplying their computational power at least since 1890 and possibly for centuries before that. I take Kurzweil's optimistic view; my rationale is that better computing power created in one generation enables us to develop a better computer with the next generation, thereby creating a positive feedback loop for an exponential growth of computing and related domains.
In the famous 1975 IEDM paper that begat Moore's Law, Gordon Moore predicted the annual doubling of chip complexity as a result of three trends, only one of which was scaling. Despite that, over the past two decades Moore's Law manifested itself mainly as a 0.7 scaling for every process node, yielding the full factor-of-two density improvement on its own.
The early days of scaling were the most rewarding. As Moore stated: "By making things smaller, everything gets better simultaneously. There is little need for trade-offs. The speed of our products goes up, the power consumption goes down, system reliability, as we put more of the system on a chip, improves by leaps and bounds, but especially the cost of doing things electronically drops as a result of the technology" (Moore, SPIE 1995). Those were the good old days. There was no need to call for a new social contract; power efficiency came naturally with scaling, as smaller transistors had smaller gate capacity and burned less dynamic power. And further efficiencies were achieved by lowering the operating voltage all the way from 5 volts to less than a volt.
But going forward with just scaling does not look as bright. Further reduction of operating voltage will cause severe reductions in performance, and further reductions in gate capacitance will have only a negligible impact on dynamic power (interconnect capacitance these days far exceeds the gate capacitance). While lithography scaling provides all the benefits with respect to the transistors, it provides none with respect to interconnect; in fact, it just gets worse. The industry had moved from two metal layers all the way to 10 metal layers, then from aluminum to copper, and recently from the convenience of SiO2 to the challenging low-k dielectric, with some even predicting air in the future. Yet the tyranny of interconnects requires us to consider other alternatives.
Next: Mobile tsunami
Calling Moore's Law a social contract is one way to look at it. Others see it as a self-fulfilling prophecy, or at least it has been so for the past 45 years. Ray Kurzweil claims it is a part of the Law of Accelerating Returns, whereby computing devices have been consistently multiplying their computational power at least since 1890 and possibly for centuries before that. I take Kurzweil's optimistic view; my rationale is that better computing power created in one generation enables us to develop a better computer with the next generation, thereby creating a positive feedback loop for an exponential growth of computing and related domains.
In the famous 1975 IEDM paper that begat Moore's Law, Gordon Moore predicted the annual doubling of chip complexity as a result of three trends, only one of which was scaling. Despite that, over the past two decades Moore's Law manifested itself mainly as a 0.7 scaling for every process node, yielding the full factor-of-two density improvement on its own.
The early days of scaling were the most rewarding. As Moore stated: "By making things smaller, everything gets better simultaneously. There is little need for trade-offs. The speed of our products goes up, the power consumption goes down, system reliability, as we put more of the system on a chip, improves by leaps and bounds, but especially the cost of doing things electronically drops as a result of the technology" (Moore, SPIE 1995). Those were the good old days. There was no need to call for a new social contract; power efficiency came naturally with scaling, as smaller transistors had smaller gate capacity and burned less dynamic power. And further efficiencies were achieved by lowering the operating voltage all the way from 5 volts to less than a volt.
But going forward with just scaling does not look as bright. Further reduction of operating voltage will cause severe reductions in performance, and further reductions in gate capacitance will have only a negligible impact on dynamic power (interconnect capacitance these days far exceeds the gate capacitance). While lithography scaling provides all the benefits with respect to the transistors, it provides none with respect to interconnect; in fact, it just gets worse. The industry had moved from two metal layers all the way to 10 metal layers, then from aluminum to copper, and recently from the convenience of SiO2 to the challenging low-k dielectric, with some even predicting air in the future. Yet the tyranny of interconnects requires us to consider other alternatives.
Next: Mobile tsunami
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LarryM99
12/23/2010 1:08 PM EST
Moore's Law is a business visualization tool, not a business plan in and of itself. It was relevant when more computing power was significant to users, but that is not really the case any more. The chip industry has got to figure out what is important to users for the next decade rather than blindly following linear thinking (even linear thinking along an exponential curve). 3D stacking is a good tool, but you have to do something useful with it.
Larry M.
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Sanjib.Acharya
12/23/2010 1:19 PM EST
Interesting article! Is this topic still in research? Is there any of the chip manufacturers actively working towards commercially deploying this technology?
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Duane Benson
12/23/2010 1:23 PM EST
If Moore's law has followed the exponential growth indicated by the law of accelerating returns, we shouldn't assume and depend on advancement continuing at that pace forever. At some point, the curve reverses and we end up moving to a point of diminishing returns. (until the next game-changing breakthrough)
It's already happening if you consider clock speed. Until recently, clock speeds were increasing as fast as anything else described by Moore's law, but they have essentially leveled out. It happened with aircraft speed, with automobile horse power and it will happen with chip density and all other aspects of semiconductors. At that point, we'll have to adapt to a world of incremental improvements rather than one of constant dramatic improvement.
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dirk.bruere
12/23/2010 3:55 PM EST
We are factors of billions, if not trillions, away from theoretical physical limits. The rest is merely engineering:-)
However, if Moore's Law were to stop so would much of the s/w industry innovations. We are just getting to the point where natural language understanding is possible - but only on supercomputers. We need the Law to continue for the next 20 years to make that economical for everyone.
As for 3D etc, whatever happened to wafer scale computing? It sounds a lot easier than 3D.
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Zeev00
12/23/2010 5:43 PM EST
Actually, what killed wafer-scale integration is yield. And that's one of the main reasons it is still dead.
Going into 3D opens up interesting new options to deal with yield issues but, in any case, 3D monolithic stacking inherently reduces the chip net area because of reduced average wire length and need of repeaters. So it will tend to help yield assuming similar defect rates.
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dirk.bruere
12/23/2010 4:45 PM EST
Well, let's say Moore's Law stopped around 1985.
You still say that s/w innovation would not have been severely impacted?
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iniewski
12/23/2010 5:43 PM EST
I wish people would just stop talking about Moore's Law. I have been hearing about it all my professional life (and I am not that young) and most of it is just too repetitive. And it is not even a law! (I am OK with Ohm's law) but a business observation. Finally, it no longer works. Can we talk about something else? Like 3D interconnects that improve performance. Without to resorting to the old Moore's Law pls. Just accept that microprocessors speeds do not increase anymore...Kris
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dirk.bruere
12/23/2010 5:57 PM EST
The generalized Moore's Law is really about processing power. I believe it is essential to keep pushing up processing power exponentially. Every order of magnitude increase brings new s/w capabilities into play. I started work when the Cray 1 supercomputer was king, at $10m (back when that was a lot of money). Now an iPhone would thrash it. That's the progress I want to continue.
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Warren
12/23/2010 8:33 PM EST
So what I find interesting is that no one seems to have an issue with the idea of twisting up technology development with "social contract" of some supposed goodness; a Moore's Law that includes improved power consumption = "Good", a Moore's Law without including improved power coonsumption = "Bad". B.S.
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tpfj
12/24/2010 10:19 AM EST
The chap who thinks we are billions if not trillions away from theoretical limits should take a look at biology for some lessons. DNA molecules are 2nm wide. Proteins are larger by a factor of 10x at best. We are currently somewhere between 40nm and 28nm. I'm not sure biology can be beaten when it comes to efficiency, so I'm gona stick my neck out and say we will settle where biology did, and for good reason. BTW, no one metioned above or in the article that power is also not scaling anymore. One more point, 3D dies means thicker chips, something the mobile industry for sure does not like. I just don't know how much thicker?
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d_sekar
12/24/2010 12:52 PM EST
Actually, monolithic 3D dice typically mean thinner chips compared to TSV ones.
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d_sekar
12/24/2010 12:54 PM EST
To add to the previous post, the mobile industry always desires small form factors, so they are stacking stuff with wire bonding even today. Going to monolithic 3D will give a thinner profile than stacking chips with wire bonding (for mobile products).
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iniewski
12/24/2010 1:12 PM EST
Yes, monolithic 3D is thinner but the power dissipation problem is worse, you need some space...To: @tpfj, I like your biology comparison as an indication where true limits might be. Biology (at least nervous system) operates at signals which are much lower than CMOS levels, as a result our amazing brain dissipates only 20W. Reducing signals levels and using analog computing is clearly a way to go to get closer to limits...Kris
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metafor
12/24/2010 4:22 PM EST
All this indicates massive spikes in both RE and NRE costs for making fabs. I know it seems like there's constant volume (with the explosion in the mobile space) to sustain this but how much longer will that last?
There's still plenty of ways to get around the ineffectiveness of 2D feature shrinking but all of them seem incredibly expensive both from an R&D point of view as well as a manufacturing equipment complexity point of view.
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d_sekar
12/24/2010 5:00 PM EST
The great part about 3D is that you can use the same litho tools and still get benefits... plus it provides a huge reduction in die size as stated in Mr. Or-Bach's article above. 3D is therefore great from a cost perspective.
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metafor
12/24/2010 11:11 PM EST
TSV and stacked 3D, yes. Monolithic 3D, not so much.
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prabhakar_deosthali
12/26/2010 1:24 AM EST
In my opinion, in the coming years the new technologies like electron spin memories and what not, the face of our industry is going to change all together and Moore's law ( or whatever you want to call it ) will be replaced by some other yardsticks ( or nano sticks should I say?). Like one of the readers has commented we have to cross may be million times on either side of the geometry we are today to really match what nature has produced. So we need new laws (of physic or business) which can predict advancement of the technologies in geometric proportions and not in linear proportions.
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wilber_xbox
12/26/2010 12:39 PM EST
I agree with you that we will soon need another yardstick to measure the growth of CMOS devices. The scaling is going to hit a wall in next decade. We will be at the scale of few hundred atoms only.
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kdboyce
12/26/2010 10:45 PM EST
Monolithic 3D chips are the way of the future. But as with all developments, it will finally be the applications that will drive the form and features thereof and dictate how the chips must be made.
The key problems now are getting rid of heat and how to efficiently handle the necessary interconnects internally and externally without killing the area/volume advantages 3D stacking of similar or dis-similar wafers can provide.
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BalaLak
12/27/2010 2:00 AM EST
How about using optics for interconnects? Will that help scale down further?
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Robotics Developer
12/27/2010 9:20 PM EST
I think that 3D is an interesting idea! I am wondering how we get enough power into the multiple devices and consequently get the heat out? Is there any cost (speed/power) associated with the connections between the "dies"? I can't help but wonder if the operating speeds and the geometries will conspire to cause system level timing issues (ringing, reflections, slow rise-times, etc). I can remember doing 3D spice simulations on packing interconnects for earlier high-speed interfaces and the difficulty with getting on/off chip with good enough signal integrity. Are there issues (or have they been solved) with the 3D stack interconnects?
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3D Guy
12/28/2010 2:16 AM EST
These are good questions. Whenever you pack more components in the same area (eg. with 3D or by scaling), you always have to deal with higher power densities and heat removal issues.
- There are many applications, eg. chips used in mobile phones and tablet computers, where power consumption is less than 1W. In these (huge) markets, power delivery and heat removal are less of an issue... so the first penetration of 3D will be there. It helps that these markets are projected to be the biggest markets for semiconductors in the next 10 years.
(to be continued in next post due to number of words restriction)
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3D Guy
12/28/2010 2:16 AM EST
- In high performance chips, eg. those used in servers, 3D will first be used to stack memory atop processors, which doesn't increase power density. Over time, as 3D becomes more mainstream, people will start stacking logic above logic, to save power, reduce cost (and/or) improve performance.
== I expect they will deal with heat removal in 3D stacked high performance chips in many ways: (1) Floorplan blocks in 3D such that a high power density block is stacked above a low power density one (2) Use dense power grids which transfer heat from various dice to the heat sink (3) Servers are moving away from using 130W individual die to using lower power cores (45W-50W) and using many more of them... this trend makes cooling easier. == In terms of tackling power delivery issues, it is less of a challenge. Companies are using many many smart techniques: (1) In multicore chips, each core has its clock referenced to its own individual power grid. eg. When the Vdd grid goes from 1V to 0.9V due to noise, the clock frequency is slightly lowered, so one doesn't need to leave so much margin for noise. (2) Freescale uses on-chip stacked capacitors that provide huge amounts of decoupling. IBM uses trench caps for eDRAM and these provide large amount of cap, which are also used for decoupling supply noise. (3) In multicore chips, when a core is shut down, its frequency is lowered slowly from 1GHz to 750MHz to 500MHz to 0MHz. This reduces the amount of supply noise. (4) There are many other solutions to the supply noise problem... the list is too long to discuss.
- In monolithic 3D, the connections between dice are very short, so their performance/power penalties are negligible.
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negative_delay_buffer
1/3/2011 7:45 PM EST
Props to @3D Guy, @Robotics Developer, and @kdboyce for getting at the heart of it.
"It's the power dissipation, stupid!"
Stacked die, monolithic 3D, and TSV all have their own unique benefits & tradeoffs, but they all have one challenge in common: power dissipation, especially from the "meat" layers between the "bread". Flip chip packages were a revolution over wirebond because they allowed better thermal dissipation away from the board, instead of injecting the heat into the board and causing warpage, thermal expansion, depopulation, etc, and you can attach a big fat heat sink to the contact surface to draw heat away. What do you do when you can no longer draw heat away equally from all layers?
There needs to be a new set of design rules for power dissipation on the internal layers, and as @RD and @3D hinted at, there needs to be some floorplanning guidelines to follow as well. EDA companies will have so much fun selling tools that can model and do STA on that, while dealing with multi-voltage and multi-temperature layers. You thought PVT and OCV analysis were nasty now, just wait. :)
For any 3D implementation to work, we'll probably need to bring in a mechanical engineer or materials engineer in on the IC Design teams in the future, to handle the new form factor, thermal expansion/contraction issues, heat distribution, and power distribution across multiple layers.
All of this means good news for us in the EE community, as there's still lots of interesting work to be done for many years to come unlocking the potential of these breakthroughs.
:sarcasm Now if you'll excuse me, I've got some patents to file on this so I can sell them to a troll so nobody can benefit from this except lawyers. end:sarcasm
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dirk.bruere
1/4/2011 4:02 PM EST
The limits to computing:
http://e3.physik.uni-dortmund.de/~suter/Vorlesung/QIV_WS01/3_PhysicalLimits.pdf
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Or_Bach
4/1/2011 4:27 AM EDT
Now that we have change our name to MonolithIC 3D Inc. we have update our web site and put a lot of interesting information including a very active blog http://www.monolithic3d.com/blog.html. I highly recommend going through it as many of the issues discussed above a re covered in details there.
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iniewski
4/1/2011 10:32 AM EDT
Interesting blog @Or_Bach, perhaps you can get Zvi or Deepak to give a talk at CMOS Emerging Technologies meeting in Whistler in June (www.cmoset.com)...kris.iniewski@gmail.com
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Simonstar
5/24/2012 12:21 AM EDT
It is an exciting time to be in the semiconductor industry because you get to see innovations and feats of engineering almost at at annual rate. Every year, people find ways to make circuits smaller and more efficient, maybe being power efficient is the way to continue Moore's Law.
Simon - http://www.starrausten.com
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