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resistion
Thanks for pointing out this detail. If this has random access as in DRAM, then ...
Volatile Memory
R_Colin_Johnson: Phase-change memory (PRAM) is not "here." Read my comments at ...
'Universal' memory aims to replace flash/DRAM
R Colin Johnson
1/20/2011 8:46 PM EST
PORTLAND, Ore.—A single "universal" memory technology that combines the speed of DRAM with the non-volatility and density of flash memory was recently invented at North Carolina State University, according to researchers.
The new memory technology, which uses a double floating-gate field-effect-transistor (FET), should enable computers to power down memories not currently being accessed, drastically cutting the energy consumed by computers of all types, from mobile and desktop computers to server farms and data centers, the researchers say.
"Memories made using our new double floating-gate structure should be about as fast as DRAM—and will need to be refreshed as often—but their densities will be about the same as flash," said EE professor Paul Franzon at NC State.
The double floating-gates use direct tunneling when storing charge to represent bits—instead of hot electron injection like flash—thus enabling operation at lower voltages. The first floating-gate in the stack is leaky, thus requiring refreshing about as often as DRAM (16 milliseconds). But by increasing the voltage its data value can be transferred to the second floating-gate, which acts more like a traditional flash memory, offering long-term nonvolatile storage.
In operation, computers using the double floating-gate FETs for their main memory can operate normally until they become idle, at which time their data values can be transferred to the second gate in order to power down the memory chip. Then when the stored values need to be accessed again by the computer, the second gate quickly transfers their stored charge back to the first gate and normal operations can resume.
"We believe our new memory device will enable power-proportional computing, by allowing memory to be turned off during periods of low use without affecting performance," said Franzon.
So far the researchers have only built the gate structures in their new FET design and are currently performing cycling testing to make sure that memories stored and retrieved from the floating gates do not cause fatigue that could eventually wear out the devices. Flash, for instance, uses voltages so high during hot-carrier injection that devices can only survive about 10,000 read/write cycles. Double floating-gate FETs use lower voltages, but only cycling testing can determine whether the devices experience excessive fatigue.
If the test devices pass cycle testing, then the researchers' next step will be to fabricate real semiconductor memories out of them—a task the researchers hope to perform by next year. Also working on the project was Neil Spigna, a research assistant professor at NC State and doctoral candidates Daniel Schinke and Mihir Shiveshwarkar. Funding was provided by the National Science Foundation.
The new memory technology, which uses a double floating-gate field-effect-transistor (FET), should enable computers to power down memories not currently being accessed, drastically cutting the energy consumed by computers of all types, from mobile and desktop computers to server farms and data centers, the researchers say.
"Memories made using our new double floating-gate structure should be about as fast as DRAM—and will need to be refreshed as often—but their densities will be about the same as flash," said EE professor Paul Franzon at NC State.
The double floating-gates use direct tunneling when storing charge to represent bits—instead of hot electron injection like flash—thus enabling operation at lower voltages. The first floating-gate in the stack is leaky, thus requiring refreshing about as often as DRAM (16 milliseconds). But by increasing the voltage its data value can be transferred to the second floating-gate, which acts more like a traditional flash memory, offering long-term nonvolatile storage.In operation, computers using the double floating-gate FETs for their main memory can operate normally until they become idle, at which time their data values can be transferred to the second gate in order to power down the memory chip. Then when the stored values need to be accessed again by the computer, the second gate quickly transfers their stored charge back to the first gate and normal operations can resume.
"We believe our new memory device will enable power-proportional computing, by allowing memory to be turned off during periods of low use without affecting performance," said Franzon.
So far the researchers have only built the gate structures in their new FET design and are currently performing cycling testing to make sure that memories stored and retrieved from the floating gates do not cause fatigue that could eventually wear out the devices. Flash, for instance, uses voltages so high during hot-carrier injection that devices can only survive about 10,000 read/write cycles. Double floating-gate FETs use lower voltages, but only cycling testing can determine whether the devices experience excessive fatigue.
If the test devices pass cycle testing, then the researchers' next step will be to fabricate real semiconductor memories out of them—a task the researchers hope to perform by next year. Also working on the project was Neil Spigna, a research assistant professor at NC State and doctoral candidates Daniel Schinke and Mihir Shiveshwarkar. Funding was provided by the National Science Foundation.
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resistion
1/21/2011 12:38 AM EST
It's still not mentioned if it's random or block access, but the combination of refresh and slow flash write is not attractive.
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PDF01
1/21/2011 2:45 PM EST
Thanks for the comments. In non-volatile mode, it has very similar properties to DRAM. The write to NV mode can be very fast compared with streaming data to an SSD.
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mifb
1/23/2011 10:10 AM EST
I realy have doubts that this gate stack can work at all. 1) For DRAM application (volatile) electron storage in the gate stack can not meet the (1e9) endurance requirement. 2) For NAND application (non-volatile) such a thick gate stack can not hace the required extended floating gate to control gate area for sufficient gate coupling ratio for working program and erase. Additionally, lots of trapping layers below the second floating gate and therefore no defined Vt and therefore very bad retention.
Seems to me authors neither understand how a reliable DRAM nor reliable NAND flash work...
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R_Colin_Johnson
1/24/2011 1:31 PM EST
You may be right, only time will tell, but the NSF thinks that they at least have a shot of pulling it off. Currently the authors are characterizing the endurance of the architecture, and if it gets over that hurdle, they will address the other doubts you have in mind. Stay tuned for the results, probably in by 2012.
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resistion
1/25/2011 8:52 AM EST
It still looks to me you will combine the DRAM leakage of first gate with the injection issues of the second NV gate. Whereas the benefits are the same as offered by alternative memories without this issue combination.
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m_gray
1/21/2011 4:13 AM EST
Not really universal, but more like a twin-memory.
I guess it is faster to store data this way, than the normal DRAM - interconnection - SSD, but this process requires a completely new access architecture ( What happens on sudden power-off? As said earlier, block or random? Which file system is best suited...)
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PDF01
1/21/2011 9:46 AM EST
Thanks for your comments. A more proper name would be "unified". It is addressed like a DRAM but transfers between volatile and non-volatile modes are done on a line by line basis. It can not cope with a sudden power-off but you could always roll back to a checkpoint stored in the device. Checkpointing would be low-overhead with this device. - Paul Franzon, NCSU
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Sanjib.Acharya
1/22/2011 4:14 AM EST
In case of sudden power loss, I agree, nothing much could be done. But usually sudden power-loss is taken care by the power supply hold-up time capacitors, which could provide extra few milliseconds for storing necessary data in the non-volatile memory. I don't know how they are planning to take care of the power-loss situation, but I believe, it is not very hard to do.
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SZA
1/21/2011 11:00 AM EST
The concept looks quite interesting. However i agree with m_gray, its a twin memory, the term Universal memory in the tile is bit misleading.
It will be interesting to know bit more details about circuit structure, what fab/process they used, some rough figures about comparing this technology with other memories... (including Universal memory candidates like MRAMs, FRAMs, PCMs etc.)
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PDF01
1/21/2011 12:25 PM EST
SZA: The paper to appear in IEEE Computer, February has many of those details. "Unified" memory is a better term. Thanks for your comments.
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SZA
1/25/2011 6:25 AM EST
@new2coding. If i understand correctly that was the first thing came in my mind too (I am an industrial PhD student and frequently argue with academic collegues on EEtimes vs IEEtimes :)).
I wonder one day academia learn something from EEtimes/UBM and create perhaps UAM (United Academics Media)or perhaps UBM aciquire IEEE/ACM!:)
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Mlstotts
1/23/2011 11:10 PM EST
This sounds very similar to Spansion's Ornand flash. I wouldn't be surprised if flash / DRAM advances are the key to competitive hardware advances in mobile computing. As we've seen in desktop and laptop computing processing power only increases the user's perception of performance so far, real-world computing performance comes from more and faster memory.
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elctrnx_lyf
1/25/2011 7:20 AM EST
Interesting concept though we should wait and see till the final cycling results are actually announced. If it can handle what both Flash and DRAM can do then probably we can work with a single unified memory in the future.
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psommerfeld
1/25/2011 4:40 PM EST
Another universal memory? I'm still waiting for the first "universal memory", phase-change memory, to come to market! Maybe the term "universal" just means "will stay in the lab forever" ;)
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psommerfeld
1/25/2011 4:41 PM EST
Oh yes, and M-RAM too! At least that's shipping in low density, but doesn't look like it will ever be economically attractive.
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R_Colin_Johnson
1/25/2011 5:38 PM EST
On the contrary, phase-change memory (PRAM) is here, although its just substituting for NOR flash so far. Our sister UBM Techinsights reported the world's first use of PRAM was last year:
http://bit.ly/gIiULt
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Volatile Memory
1/25/2011 6:51 PM EST
R_Colin_Johnson: Phase-change memory (PRAM) is not "here." Read my comments at the URL you mentioned! Your sister company, UBM Techinsights, was simply the victim of an elaborate scam. The phone unit they tested was a fake, non-commercial unit. Samsung did indeed have PRAM in the original specs for that phone line, but later abandoned PRAM due to power-consumption issues. Thus, it appears, the only cell phone with PRAM in the world was destroyed by UBM Techinsights. You don't believe me? Buy a Samsung GT-E2550 or GT-E2550L Monte Slider and see what's inside. I did. It has NOR and absolutely no PRAM. No commercial product on the market, other than a couple of development boards, uses PRAM or PCM. Please do not perpetuate the Techno-Ponzi!
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DF
1/25/2011 5:47 PM EST
The article is somewhat misleading in that it says that Flash uses hot electron injection.
NOR flash uses that, but NAND flash uses tunneling, like this memory does. The tunneling gives NAND flash more rewrite cycles than NOR flash as a result, but there’s still a finite lifetime for the NAND flash, ranging from 10,000 cycles (for MLC devices) upwards of 1,000,000 cycles (for the best SLC devices).
In short, I don’t really see the benefit of this technology outside of a few niche applications. In general, it should be possible just to put a DRAM die and a NAND flash on a single package and just write over the DRAM’s contents to the NAND flash when suspending.
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resistion
1/26/2011 12:17 AM EST
Thanks for pointing out this detail. If this has random access as in DRAM, then it could be wired like a NOR. Although normally NOR uses hot carrier injection for programming, it still has to tunnel (Fowler-Nordheim) to erase. I still call this an injection process, with issues such as SILC. So that is why Flash has the lowest reliability of all memories.
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