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Cadence rolls 28-nm digital design flow
1/31/2011 12:42 PM EST
SAN FRANCISCO—EDA vendor Cadence Design Systems Inc. Monday (Jan. 31) rolled out an end-to-end digital design flow for 28-nm based on the company's Encounter platform.
According to Cadence (San Jose, Calif.), the new Encounter-based flow provides a faster, more deterministic path to achieve giga-gate/gigahertz silicon through technology integration and significant core architecture and algorithm improvements in a unified design, implementation and verification flow. The flow, available immediately, works seamlessly with Cadence’s analog/mixed-signal and silicon/package co-design domains, Cadence said.
“Twenty-eight-nanometer process technology is both a great opportunity and challenge for designers, with its power, performance and area advantages coupled with challenges such as process variation and new manufacturing effects,” said Albert Li, director of design and development at Global Unichip Corp.
Li said Global Unichip used the Cadence flow for its first 28-nm design. Using the Cadence flow, enabled Global Unichip to handle the complex routing, variability and manufacturing requirements of 28-nanometer designs, as well as tackle 100+ million gate designs within a reasonable design cycle time, according to Li.
Eliminating the need for tradeoffs between complexity and advanced process nodes, the new flow optimizes complex design at 28-nm, providing a path for advanced SoC development to realize the cost benefits of smaller geometries, Cadence said. Key to the flow’s performance is a unified digital design, implementation, and verification based on intent, abstraction, and convergence, the company said.
The Encounter-based Silicon Realization digital end-to-end flow includes technologies such as Encounter RTL Compiler, Encounter Digital Implementation System, Encounter Conformal technologies, Encounter Test, Encounter Timing System, Cadence QRC Extraction, Encounter Power System and Encounter DFM technologies, Cadence said.
The new flow includes features to enhance unified intent, enhance abstraction and provide faster convergence, Cadence said. It also includes fully-integrated 3D-IC capabilities, the company said.
Cadence said the flow supports the company's Silicon Realization approach, a key element of the company's EDA360 vision.
According to Cadence (San Jose, Calif.), the new Encounter-based flow provides a faster, more deterministic path to achieve giga-gate/gigahertz silicon through technology integration and significant core architecture and algorithm improvements in a unified design, implementation and verification flow. The flow, available immediately, works seamlessly with Cadence’s analog/mixed-signal and silicon/package co-design domains, Cadence said.
“Twenty-eight-nanometer process technology is both a great opportunity and challenge for designers, with its power, performance and area advantages coupled with challenges such as process variation and new manufacturing effects,” said Albert Li, director of design and development at Global Unichip Corp.
Li said Global Unichip used the Cadence flow for its first 28-nm design. Using the Cadence flow, enabled Global Unichip to handle the complex routing, variability and manufacturing requirements of 28-nanometer designs, as well as tackle 100+ million gate designs within a reasonable design cycle time, according to Li.
Eliminating the need for tradeoffs between complexity and advanced process nodes, the new flow optimizes complex design at 28-nm, providing a path for advanced SoC development to realize the cost benefits of smaller geometries, Cadence said. Key to the flow’s performance is a unified digital design, implementation, and verification based on intent, abstraction, and convergence, the company said.
The Encounter-based Silicon Realization digital end-to-end flow includes technologies such as Encounter RTL Compiler, Encounter Digital Implementation System, Encounter Conformal technologies, Encounter Test, Encounter Timing System, Cadence QRC Extraction, Encounter Power System and Encounter DFM technologies, Cadence said.
The new flow includes features to enhance unified intent, enhance abstraction and provide faster convergence, Cadence said. It also includes fully-integrated 3D-IC capabilities, the company said.
Cadence said the flow supports the company's Silicon Realization approach, a key element of the company's EDA360 vision.
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