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DesignCon panel mulls over delayed design skeds
Nicolas Mokhoff
2/1/2011 6:19 AM EST
SANTA CLARA, Calif. -- At DesignCon here a panel of four designers from Broadcom, Nvidia, Netlogic, and Juniper Networks, agreed that designs need to meet different "good enough" specs for different markets.
The panelists gathered to discuss what methodologies could speed up design schedules. They agreed that design cycles vary across design teams and the design windows for one type of design are markedly different from that of another.
If the design is for backend communications it needs to be rugged and therefore meet those design criteria which might require today’s usual 12 to 18 months. But in designing a consumer phone with features that match and exceed those of competitors, designers need to address a narrower design window, -- on the order of six months--, to stay competitive with other consumer electronics companies.
"As we try to wrap up ever more complex designs in less and less time, the risks that prevent design closure are increasing almost exponentially,” said Sunil Malkani, director of IC Design Engineering at Broadcom. "And you can’t get away from the fact that verification takes the most time in a design."
"It is hard to generalize on the windows of design," said Ramon Marcias, director of physical design, Processor Group at NetLogic Microsystems. "There is no dramatic way to speed up designs in the back end." NetLogic provides semiconductor solutions for the network enterprise space.
"A week to iterate through your flow to fix a design bug like a bad timing exception or a metastability issue is bearable in a multi-year project," said John Busco, senior manager, Design Implementation at Nvidia, "it doesn’t fly in the face of a multi-month project."
Busco was sympathetic to Intel’s woes reported this week on recalling its latest chips for a design flaw. "That can be astronomically expensive. I know--we have been there."
"The most serious 'chip stoppers' are the ones least likely to be caught using commonly used simulation or STA [static timing analyzer]-based techniques," said Ravi Damaraiu, ASIC Director at Juniper Networks. "Using old techniques to catch these problems will no longer cut it when a few days delay may cause you to miss a market window. At Juniper we apply verification to silicon before RTL—register transfer level-- tape out."
What are some of the needed approaches to speed up tape outs for any market? Damaraiu said "small integrated design teams are optimum, and management allowing freedom to the teams, as long as they define a few things in common that must be adhered to."
"Maybe you have a core team design the 'feeds' and 'speeds' of a loaded chip, and then have tier 2 teams do the derivatives of the chip," said Invidia’s Busco.
Another bugaboo is the tools. Panelists agreed that design tools need to be reengineered with parallel processing to speed up designs. The only design tool vendor on the panel and panel organizer Bernard Murphy, CTO at Atrenta, had his take on that: "Consumer devices is a very enticing market but it turns the world upside down for the designer: how does one design a chip in a tight design window that we can sell a million of." For these consumer mobile devices one needs tools that empower the designer with early hardware/software co-simulation that addresses low power designs. “In the next five years, power estimation will play a crucial role."
Atrenta tools and methodologies are geared for capturing design intent and for optimizing designs early in the design cycle before detailed implementation.
One point the designer panel agreed on is that the notorious duality in design standards drive "designers crazy and are a waste of time," according to Nvidia's Busco. "There needs to be an industry-wide objective body that can work out one set of standards for a typical design flow in order to not force designers to choose one company’s design library over another's, for example," said Broadcom's Malkani.
The issues presented by designers at this DesignCon panel need to be raised in a larger 'social network' environment, maybe in a Facebook group of IC designers, OEMs, and standards writers, in order to cast a wider net for designers on the fringe to have a say in these matters.
The panelists gathered to discuss what methodologies could speed up design schedules. They agreed that design cycles vary across design teams and the design windows for one type of design are markedly different from that of another.
If the design is for backend communications it needs to be rugged and therefore meet those design criteria which might require today’s usual 12 to 18 months. But in designing a consumer phone with features that match and exceed those of competitors, designers need to address a narrower design window, -- on the order of six months--, to stay competitive with other consumer electronics companies.
"As we try to wrap up ever more complex designs in less and less time, the risks that prevent design closure are increasing almost exponentially,” said Sunil Malkani, director of IC Design Engineering at Broadcom. "And you can’t get away from the fact that verification takes the most time in a design."
"It is hard to generalize on the windows of design," said Ramon Marcias, director of physical design, Processor Group at NetLogic Microsystems. "There is no dramatic way to speed up designs in the back end." NetLogic provides semiconductor solutions for the network enterprise space.
"A week to iterate through your flow to fix a design bug like a bad timing exception or a metastability issue is bearable in a multi-year project," said John Busco, senior manager, Design Implementation at Nvidia, "it doesn’t fly in the face of a multi-month project."
Busco was sympathetic to Intel’s woes reported this week on recalling its latest chips for a design flaw. "That can be astronomically expensive. I know--we have been there."
"The most serious 'chip stoppers' are the ones least likely to be caught using commonly used simulation or STA [static timing analyzer]-based techniques," said Ravi Damaraiu, ASIC Director at Juniper Networks. "Using old techniques to catch these problems will no longer cut it when a few days delay may cause you to miss a market window. At Juniper we apply verification to silicon before RTL—register transfer level-- tape out."
What are some of the needed approaches to speed up tape outs for any market? Damaraiu said "small integrated design teams are optimum, and management allowing freedom to the teams, as long as they define a few things in common that must be adhered to."
"Maybe you have a core team design the 'feeds' and 'speeds' of a loaded chip, and then have tier 2 teams do the derivatives of the chip," said Invidia’s Busco.
Another bugaboo is the tools. Panelists agreed that design tools need to be reengineered with parallel processing to speed up designs. The only design tool vendor on the panel and panel organizer Bernard Murphy, CTO at Atrenta, had his take on that: "Consumer devices is a very enticing market but it turns the world upside down for the designer: how does one design a chip in a tight design window that we can sell a million of." For these consumer mobile devices one needs tools that empower the designer with early hardware/software co-simulation that addresses low power designs. “In the next five years, power estimation will play a crucial role."
Atrenta tools and methodologies are geared for capturing design intent and for optimizing designs early in the design cycle before detailed implementation.
One point the designer panel agreed on is that the notorious duality in design standards drive "designers crazy and are a waste of time," according to Nvidia's Busco. "There needs to be an industry-wide objective body that can work out one set of standards for a typical design flow in order to not force designers to choose one company’s design library over another's, for example," said Broadcom's Malkani.
The issues presented by designers at this DesignCon panel need to be raised in a larger 'social network' environment, maybe in a Facebook group of IC designers, OEMs, and standards writers, in order to cast a wider net for designers on the fringe to have a say in these matters.
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