450-mm brings confusion to supply chain

Soaring fab costs
Despite the improvement in business, fewer companies are willing to throw down the money to build new, greenfield plants. One reason is that fab costs are soaring out of control.

At one time, a leading-edge 300-mm fab was about $3 billion to $5 billion. Now, Toshiba Corp. may have set the record for the world’s most expensive fab. The company’s new 300-mm NAND plant (Fab 5), including construction costs, is expected to run $10.5 billion to $11.5 billion, according to SEMI.

At the recent Industry Strategy Symposium (ISS), sponsored by SEMI, Robert Bruck, vice president of the Technology and Manufacturing Group at Intel Corp., said a 450-mm fab could run $10 billion. That figure may not include construction costs.

The R&D costs to develop a 22-nm process is expected to run from $999 million to $1.354 billion, compared to $581 million to $796 million at 32-nm, according to Handel Jones, CEO of International Business Strategies Inc. At 90-nm, the R&D cost ranged from $198 million to $283 million, Jones said.

Fab tool costs are also soaring, especially lithography. In the 1980s, a leading-edge lithography scanner sold for about $1 million. Today, ASML Holding NV’s  193-nm immersion scanners run $40 million each. And a production-worthy extreme ultraviolet (EUV) tool could sell for about $125 million-if or when these machines are shipped.

Photomask costs are also increasing. A 45-nm ''mask set'' runs about $800,000 to $900,000, but a 32/28-nm ''mask set'' could run $2 million or so, according to one photomask vendor.  A 22-nm ''mask set'' could double, according to some.

Needless to say, IC design costs are soaring out of control. ''With each successive node the cost of a design goes up,’’ said Piper Jaffray’s Richard. ‘’The cost of a 45-nm SOC chip design is estimated to be roughly $80 million and a 32-nm SOC is $130 million. We estimate that the addressable market of these chips needs to be roughly $400 million and $650 million to make a reasonable return assuming a 50% gross margin.’’   
       
The cost to move from 300-mm to 450-mm fabs is also expected to be enormous. Every 15 years or so, the industry has moved to a new wafer size, ostensibly to stay on Moore’s Law. The transition to a new wafer size has already been bumpy, especially in 300-mm, when fab companies announced and then delayed a plethora of plants several years ago. The fab tool makers developed the first round tools for these plants, but were left holding the bag-and suffered massive losses-when the fabs were delayed.

For some time, four chip makers-Intel, Samsung, TSMC, and, to some degree, Toshiba-have been pushing the industry towards the 450-mm era. IDMs wanted 450-mm pilot lines as early as 2012.

In the beginning, most fab tool vendors refused to invest in 450-mm for several reasons. The return-on-investment remains unclear and no one is sure who will pay for the R&D. And fab tool vendors do not want to repeat the same mistakes in the early days of the 300-mm era.
    
Then, suddenly, Intel recently announced the D1X fab in Oregon, a plant that is  capable of producing 300-mm wafers and is ''450-mm capable.’’ The startup time for D1X is 2013.
 
Last week, TSMC officially disclosed plans that it will build a 450-mm fab, according to an analyst. The first 450-mm line is planned for Fab 12 Phase VI; it will be for their 20-nm production ramp, according to VLSI Research. TSMC’s 450-mm pilot line is expected to start around 2013 to 2014, with production due in 2015 to 2016, according to the firm.