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Accellera approves verification standard
2/21/2011 3:18 PM EST
SAN FRANCISCO—EDA standards development organization Accellera said Monday (Feb. 21) it has approved version 1.0 of its Universal Verification Methodology (UVM) standard.
The UVM standard establishes a methodology to improve design and verification efficiency, verification data portability and tool, and verification IP interoperability, according to Accellera. The standard is based on Open Verification Methodology, a verification methodology developed in 2007 by Cadence Design Systems Inc. and Mentor Graphics Corp.
"UVM puts in place a single, open standard to advance verification productivity within design teams and across multi-company design and verification collaborative efforts," said Shishpal Rawat, Accellera chair, in a statement.
The UVM standard, developed by Accellera's verification IP technical subcommittee, is available as the class reference manual accompanied by an open-source SystemVerilog base class library implementation and a user guide, Accellera (Napa, Calif.) said.
According to Accellera, UVM 1.0 fully qualifies the baseline features, corrects most of the known bugs and implements enhancement requests. Major new features include a phasing mechanism, a register package (derived from Verification Methodology Manual technology) and support for the Open SystemC Initiative's Transaction Level Modeling-2.0 (TLM-2.0) standard to model component transaction connectivity and communication, Accellera said.
Mentor issued a statement Monday promising comprehensive support for UVM 1.0. Cadence, Synopsys Inc. and verification-focused EDA vendor Aldec Inc. supported the early access version of UVM 1.0 and are expected to support the final version of the standard.
Cadence last month announced more than 600 new capabilities to help boost verification productivity for ASIC and FPGA designers, coupled with full support for UVM 1.0 industry standard.
The UVM standard establishes a methodology to improve design and verification efficiency, verification data portability and tool, and verification IP interoperability, according to Accellera. The standard is based on Open Verification Methodology, a verification methodology developed in 2007 by Cadence Design Systems Inc. and Mentor Graphics Corp.
"UVM puts in place a single, open standard to advance verification productivity within design teams and across multi-company design and verification collaborative efforts," said Shishpal Rawat, Accellera chair, in a statement.
The UVM standard, developed by Accellera's verification IP technical subcommittee, is available as the class reference manual accompanied by an open-source SystemVerilog base class library implementation and a user guide, Accellera (Napa, Calif.) said.
According to Accellera, UVM 1.0 fully qualifies the baseline features, corrects most of the known bugs and implements enhancement requests. Major new features include a phasing mechanism, a register package (derived from Verification Methodology Manual technology) and support for the Open SystemC Initiative's Transaction Level Modeling-2.0 (TLM-2.0) standard to model component transaction connectivity and communication, Accellera said.
Mentor issued a statement Monday promising comprehensive support for UVM 1.0. Cadence, Synopsys Inc. and verification-focused EDA vendor Aldec Inc. supported the early access version of UVM 1.0 and are expected to support the final version of the standard.
Cadence last month announced more than 600 new capabilities to help boost verification productivity for ASIC and FPGA designers, coupled with full support for UVM 1.0 industry standard.
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