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unknown multiplier
A company like Intel must favor the SoC approach as it enables the autocratic ...
satya_ibm
I dont think Intel Integrated graphics can beat AMD's in near future. AMD ...
Intel details Sandy Bridge at ISSCC
Dylan McGrath
2/23/2011 1:04 AM EST
Minimize power consumption
Because Sandy Bridges' x86 cores and L3 cache share the same power plane, Intel faced the challenge that the minimum voltage needed to keep the L3 cache data may have limited the minimum operating voltage of the cores, increasing the power consumption of the system, according to the paper. Intel got around this issue by developing several circuit and logic design techniques to minimize the minimum operational voltage of the L3 cache and the register files of the chip to bring it to a lower level than the core logic, according to the paper.
"One of the design targets was to minimize as much as possible power consumption," Knoll said.
One of the techniques used to skirt the issue was a shared p-channel MOSFET technique that weakens the memory cell pull up device effective strength that solves the problem of RF write-ability degradation at low voltages that can be created by manufacturing process variations, Knoll said.
"With such techniques we are able to improve the minimum operating voltage for a vast majority" of the chip, Knoll said.
Thanks to the use of these design techniques, Sandy Bridge's power dissipation ranges from 95W for a four-core device operating in a high-end desktop to17W for a two-core Sandy Bridge running an optimized mobile product, according to the paper.
Sandy Bridge also introduces a debug bus that allows monitoring the traffic between the x86 cores, GPU, caches and system agent on the processor internal ring, according to the paper. The bus, dubbed the Generic Debug eXternal Connection (GDXC), allows chip, system or software debuggers to sample ring data traffic as well as ring protocol control signals and drive it to an external logic analyzer, where it can be recovered and analyzed, according to the paper.
"The GDXC is a valuable tool for system and software debuggers," Knoll said.
Sandy Bridge also includes two different types of thermal sensors to monitor the temperature of the die, according to the paper. One is a diode-based thermal sensor on each core that compares the diode voltage to output the temperature, providing information for throttling, catastrophic function and fan regulation. The second is a much smaller CMOS-based thermal sensor with a more limited temperature range that can be placed at several locations inside the core to provide an accurate picture of core hot spots, according to the paper.
Earlier this year, Intel discovered a design flaw in one of the support chips for the first quad-core version of Sandy Bridge that began shipping Jan. 9. The company came up with a quick fix for the issue and temporarily halted shipments of the support chip. Intel later resumed shipments of the flawed chip to PC suppliers that were implementing it in systems were the flaw would not be an issue.
Because Sandy Bridges' x86 cores and L3 cache share the same power plane, Intel faced the challenge that the minimum voltage needed to keep the L3 cache data may have limited the minimum operating voltage of the cores, increasing the power consumption of the system, according to the paper. Intel got around this issue by developing several circuit and logic design techniques to minimize the minimum operational voltage of the L3 cache and the register files of the chip to bring it to a lower level than the core logic, according to the paper.
"One of the design targets was to minimize as much as possible power consumption," Knoll said.
One of the techniques used to skirt the issue was a shared p-channel MOSFET technique that weakens the memory cell pull up device effective strength that solves the problem of RF write-ability degradation at low voltages that can be created by manufacturing process variations, Knoll said.
"With such techniques we are able to improve the minimum operating voltage for a vast majority" of the chip, Knoll said.
Thanks to the use of these design techniques, Sandy Bridge's power dissipation ranges from 95W for a four-core device operating in a high-end desktop to17W for a two-core Sandy Bridge running an optimized mobile product, according to the paper.
Sandy Bridge also introduces a debug bus that allows monitoring the traffic between the x86 cores, GPU, caches and system agent on the processor internal ring, according to the paper. The bus, dubbed the Generic Debug eXternal Connection (GDXC), allows chip, system or software debuggers to sample ring data traffic as well as ring protocol control signals and drive it to an external logic analyzer, where it can be recovered and analyzed, according to the paper.
"The GDXC is a valuable tool for system and software debuggers," Knoll said.
Sandy Bridge also includes two different types of thermal sensors to monitor the temperature of the die, according to the paper. One is a diode-based thermal sensor on each core that compares the diode voltage to output the temperature, providing information for throttling, catastrophic function and fan regulation. The second is a much smaller CMOS-based thermal sensor with a more limited temperature range that can be placed at several locations inside the core to provide an accurate picture of core hot spots, according to the paper.
Earlier this year, Intel discovered a design flaw in one of the support chips for the first quad-core version of Sandy Bridge that began shipping Jan. 9. The company came up with a quick fix for the issue and temporarily halted shipments of the support chip. Intel later resumed shipments of the flawed chip to PC suppliers that were implementing it in systems were the flaw would not be an issue.
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LordTwaroog
2/23/2011 2:44 AM EST
Question: How does the p-channel sharing technique work?
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jnhong
2/23/2011 10:15 AM EST
Interesting. It is likely a large, distributed PFET to modulate VDD into every bitcell. It throttles the power to every cell in a row when a write op is performed. That's the easy part.
The interesting part is this pfet is "shared", so it could also affect the neighboring row of bitcells, which may lose their data when VDD is dropped. Or not, depending on leakage and noise. Another ISSCC paper should reveal more details.
I originally thought it switched VDD, but reading closely, it implies VDD modulation, rather than on/off. The technique has significant layout impact -- the 6T cell becomes 8T equivalent and layout symmetry is very much compromised.
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LordTwaroog
2/24/2011 1:35 AM EST
Thanks for a bit of idea - I'll explore this soon.
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kinnar
2/23/2011 12:44 PM EST
This is a highly awaited information about the Architecture from Intel and it is good that Intel has started providing some technical information. By the time Haswell Architecture comes in usage the might get complete information about Sandy Bridge.
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goafrit
2/23/2011 7:44 PM EST
The more you look, the less you see. It is free press, I doubt if they disclosed anything new. Just telling AMD to shut down because they have moved on.
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satya_ibm
2/24/2011 2:25 AM EST
I dont think Intel Integrated graphics can beat AMD's in near future. AMD graphics is way ahead of Intels. Response from Intel's Graphics is too slow compared to AMD/ATI. I have Wii also, amaging quality. Also see latest HP product dm1z with AMD latest processor which has integrated graphics processor, what an amaging product.
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unknown multiplier
6/19/2011 12:13 PM EDT
A company like Intel must favor the SoC approach as it enables the autocratic control over the final system product, in contrast to SiP, where it has to depend on other companies' supplied parts.
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