PARIS – Cadence Design Systems Inc. announced it has opened and extended its portfolio of verification IP and memory models to support silicon to system development.
Cadence said its verification IP (VIP) Catalog now supports major third-party simulators, incorporates memory models and VIP obtained from Denali's acquisition and features expanded protocol availability. The company claimed it is enabling users to more quickly and efficiently verify the standard part of their design at all stages of the design process.
In an interview with EE Times
, Susan Peterson, director, Verification IP Product Management, Cadence Design Systems Inc., declared: "What we have noticed over the past decade is that, as more standards become available, the percentage of content in an SoC is getting higher and higher. It is too hard to verify from scratch as it requires too much time, effort and expertise. Customers can now find industry standard verification IPs and memory models to offload that part of the verification process and free them up to look at more differentiated parts of their design. It also frees them from having to be an expert in all of these protocols because there is a lot of knowledge embodied in each of the verification IP and memory models."
Peterson outlined that Cadence's announcement is the result of the last eight months or so of work to bring together the Cadence verification IP portfolio and the Denali verification IP and memory model portfolio.
Asked if it is the materialization of Denali's acquisition mid-May 2010
, she replied affirmatively but specified that today's announcement relates to Denali's verification IP and memory models. The other part of their business is the design IPs.
"Verification IP is different from design IP," she explained. "Design IP is content, RTL code that you put in your design and becomes part of your design. Instead, verification IP stimulates your design, looks at the results and makes sure that those results are compliant with the protocol specifications."
Memory models are special kinds of verification IPs, she continued. "What they add is a layer that has information specific to each datasheet. Memory models did not change from what Denali was providing. Denali was considered to be the de facto standard in memory models with support for over 15,000 configurations, and customers told us they loved the interface, the pricing, the packaging. So we did not change much. We are leveraging Denali's strengths."
Cadence's VIP catalog now provides third-party simulation support that enables customers to deploy Cadence VIP across existing environments, the company claimed.
In a commentary, Peterson declared: "One of the key capabilities is that it supports third-party simulators across the industry. This is an illustration of our EDA360 philosophy that, with the verification IP and memory models, brings the content to help realize the design. This is available across the industry not just to Cadence's users."
The VIP and memory models indeed run on the Cadence Incisive Enterprise Simulator and also the Synopsys VCS and Mentor Graphics Questa simulators.
In addition to memory models and VIP gained from Denali's acquisition, Cadence said the expanded offering boasts support of emerging protocols such as the AMBA4 family, the latest MIPI protocols (M-PHY, DigRF and UniPro), PCI Express Gen 3, SuperSpeed USB and Ethernet 40/100G, as well as ne memory models including DDR4, LRDIMM and Flash ONFI 3.0.
In total, Cadence's VIP catalog covers more than 30 complex and emerging protocols but Peterson said Cadence is constantly updating its coverage. It is currently working on a new MIPI protocol called LLI.
Peterson noted that her question to designers is always: "Please, can you give us some insights about what protocols you are working on right now, and in most cases, we realize that we have pretty much everything they can think of for their SoC, everything from the more commonly used protocols to more specific protocols. We certainly have an advantage in terms of number of protocols we provide."
Cadence is also announcing new use models, including system validation with new accelerated VIP that addresses hardware/software integration and a new SoC portfolio that makes SoC verification more cost effective, as well as a roadmap for extending the solution to enable software-driven verification, a new approach providing a programmer's view of system verification.
"Probably the most unique part of the news is some new use models that are put in place and that help our users move more smoothly from silicon implementation or IP development through SoC and system development where we are incorporating some of the software and reusing your environment, your verification and memory models along the way."
In conclusion, Peterson said her message to design teams –although it sounds a little marketing- is: "Don't worry, be happy! We've got you covered no matter what protocol you need, what memory you use, how expert your team is, no matter the stage of the design process, what testbench language you use and also whatever simulator you use. Many customers have one project that uses Synopsys' VCS, one project that uses Cadence and another that uses Mentor's simulator. With Denali, they could use one verification IP for all projects. This is the kind of things we are now opening to them. Supporting third-party simulators is a real differentiator for us."
Both IP web portals, Design & Reuse SA
(D&R) and ChipEstimate
, will benefit from Cadence VIP's expansion, Peterson said.
To access Cadence VIP Catalog, click here