Intel: EUV late for 10-nm milestone
2/28/2011 9:02 PM EST
Design rules rule
At Intel, the company used dry 193-nm lithography at the 45-nm node. Then, at 32-nm, it inserted its first 193-nm immersion tools for production, mainly from Nikon.
At 22-nm, Intel will continue to use 193-nm immersion lithography. The chip giant is expected to use both ASML and Nikon for the critical layers for its 22-nm node, which will go into production in the second half of 2011.
Then, at 14-nm, the chip maker will continue to use 193-nm immersion, plus a double-patterning technique called pitch splitting. In some conferences, Intel has talked about using quintuple patterning at 14-nm. The company hopes to set up an EUV pilot line for the 14-nm node, but it’s unclear if EUV will be ready in time.
In any case, Intel has already defined and finalized its design rules for the 14-nm node-some two years before the devices move into production. The design rules for 14-nm are ''frozen,’’ Sivakumar said.
At 65-nm and above, Intel used 2-D random and complex layouts in chip design. Scaling 2-D random layouts are difficult at 45-nm. So, starting at 45-nm, Intel moved towards 1-D unidirectional, gridded design rules, he said.
For the 10-nm node, Intel hopes to use 193-nm immersion for the non-critical layers and EUV for the more complex and finer line cut steps. ''EUV is our primary option’’ in those steps, he said. If EUV is not ready, Intel may use maskless or 193-nm immersion to handle the line cut steps.
In any case, Intel has already defined its design rules for 10-nm, which will be based on a 1-D unidirectional, gridded scheme. But here’s the dilemma: Intel’s 10-nm design rules must adhere to either an EUV-centric world or a 193-nm immersion scheme-not both, he said.
EUV is late for the design rule definition stage for Intel’s 10-nm node, he said. Intel has reportedly started to devise its design rules based on 193-nm immersion and a multiple-patterning scheme.
When the EUV tools are ready, Intel could backtrack and re-define the design rules. So, in effect, there is still time for EUV to be inserted at the 10-nm node, he said. If the tools are not ready, Intel must look at other options. The company’s 10-nm design rules will be officially frozen in the first quarter of 2013.