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peter.clarke
DrQuine
I'm baffled. What about the elephant in the room? The performance of mainstream ...
Anobit battles 'plummeting' flash endurance
Peter Clarke
3/8/2011 11:20 AM EST
LONDON – Anobit Technologies Ltd. has said it has begun high volume production of its MSP2020 NAND flash memory controller in cooperation with Hynix Semiconductor Inc. It has also brought forward a supporter that says its IC can help address NAND flash memory that has been reduced to 3,000 read/write cycles in leading-edge devices.
Anobit was founded in 2006 to make solid-state drives. It's MSP (Memory Signal Processing) technology is a combination of error correction and memory management schemes that compensates for errors and evens out wear thereby allowing higher apparent performance.
The MSP2020 supports up to two ONFI-compliant NAND interfaces to a host processor, and can support product configurations from 4- to 128-Gbytes. As such the MSP2020 is suitable for high-performance mobile computing devices. It enables the use of commercial-grade two-bits-per-cell and three-bits-per-cell NAND flash within endurance- and performance-intensive embedded computing applications.
"In the span of just five years, the endurance of mainstream NAND flash has plummeted from 100,000 program/erase cycles to approximately 3,000 cycles, and the industry push toward three-bit-per-cell MLC NAND will place further downward pressure on NAND endurance. In parallel, mobile computing devices will continue to fuel demand for higher NAND endurance and performance," said Gregory Wong, founder and principal analyst, Forward Insights, in a statement issued by Anobit (Herzeliya, Israel). "Anobit's innovative MSP technology is well positioned to close the NAND endurance gap, and in so doing, help fuel the proliferation of NAND flash memory into a variety of consumer electronics and computing markets."
"The MSP2020 flash controller has been qualified for production with Hynix 2xnm MLC NAND by one of our key customers," said J.S. Yang, Hynix vice president of engineering, in the same statement.
Related links and articles:
www.anobit.com
News articles:
Intel funds SSD maker Anobit
Flash startup gains funding
Samsung, Seagate develop flash drive controllers
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Robotics Developer
3/8/2011 3:18 PM EST
It sounds good but not sure. What will the endurance numbers be if their chip is used? The article is a nice marketing piece with no information. I was hoping to see some numbers so that the improvement was understood and not just "better". Is this too early in the development cycle for any measurements to have been made or available?
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Dror Salee
3/8/2011 3:36 PM EST
This product is shipping in volume.
Endurance meets the customer/application needs.
In Smartphones, it is typically in the low thousands program/erase (P/E) cycles plus 1yr retention. Anobit has announced an enterprise SSD which meets endurance spec which is equivalent to 50,000 P/E cycles, using standard off-the-shelf MLC NAND, typically spec'd at 3,000 P/E cycles. I hope this helps. Dror Salee, Anobit
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Robotics Developer
3/8/2011 10:44 PM EST
Yes, thank you!! I love hearing the details that sounds like quite an improvement. I would have put that into the brief press releases and articles to really stir up interest.
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Dror Salee
3/9/2011 4:21 AM EST
You are correct... It is in mentioned in the press release, but not always picked up by the press.
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Code Monkey
3/8/2011 3:47 PM EST
Wear leveling and FEC are nothing new in SD cards, thumb drives and SSDs. Otherwise, the FAT table (written every time you write to a file) wouldn't last long. A flash manager needs to remember sectors that go bad, provide wear leveling, and do forward error correction among other things. A press release wouldn't necessarily say "Ours is better than Theirs because...".
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Dror Salee
3/8/2011 4:14 PM EST
You are correct about wear leveling and error correction codes. This product has something else, which we call Memory Signal Processing. It is about applying signal processing methods to the analog voltage levels inside the memory array.
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PTCHIANG
3/9/2011 1:20 AM EST
Does MSP tuned voltage levels mean any reduction in MLC's capacity(density) for the user? costs in exchange for a better endurance.
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Dror Salee
3/9/2011 4:20 AM EST
Absolutely no. MSP is all about using mathematics to help the physics.
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HAL..4
12/14/2011 10:41 AM EST
Poor endurance is just one aspect of newer NAND devices that is problemmatic. The other is increasing latency because of the much slower multi-level cells and the the increasing time neeeded for error correction before any of the retrieved data can be used. Cell latency used to be of the order of 20-30uS and 1-bit error correction added almost nothing to that. Now cell latency is 80uS or more and typical NAND controllers add far more.
Our application, which demands low random access latency, used to be practical with NAND but with present trends, may become impractical before we can deliver a product. Does the MSP controller help the latency issue?
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peter.clarke
12/14/2011 11:07 AM EST
@HAL..4
I don't know about latency.
The fact they don't mention it suggests maybe not.
In fact the clever MSP stuff my increase latency.
If you find out please share with the group.
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DrQuine
12/15/2011 7:27 AM EST
I'm baffled. What about the elephant in the room? The performance of mainstream NAND has dropped to 3% of its previous value. WHY?
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peter.clarke
12/15/2011 9:34 AM EST
@DrQuine
What metric of performance are you using?
Read speed?
Write speed?
And what are your absolute measurements?
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