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Xilinx launches next-gen ISE design suite
Dylan McGrath
3/8/2011 2:26 PM EST
SAN FRANCISCO—Programmable logic vendor Xilinx Inc. Tuesday (March 8) announced the immediate availability of the latest version of its ISE Design Suite, ISE 13, featuring enhancements to improve productivity and progression towards true plug-and-play IP that targets the company's Spartan-6, Virtex-6 and 7 series FPGAs.
ISE Design Suite 13 introduces accelerated verification, plug-and-play IP with IP-XACT support and a new team design methodology that shortens design cycles with timing repeatability for multiple engineers working in parallel, according to Xilinx (San Jose, Calif.).
According to Xilinx, ISE 13 also emphasizes speeding the verification process—which now accounts for over half of design cycle time—with a new hardware co-simulation capability and AMBA4 AXI4 bus functional simulation models. Leveraging Xilinx's portfolio of development boards, kits and Xilinx's ISE Simulator, design teams can now accelerate simulation runs that previously would take hours into minutes, according to the company. Through real-time simulation, verification engineers can test implemented blocks of the design while leaving other blocks that are still under development in the simulator accelerating overall verification by up to 100 times faster than native simulation, Xilinx said.
Also new to ISE 13 is a team design methodology, which addresses the challenge of multiple engineers working on a single project by providing a methodology for group of developers to work in parallel, according to Xilinx. Building on the design preservation capability made available in ISE 12, the team design flow provides additional functionality and allows early implementation results on completed portions of the design to be locked down without having to wait for the rest of the design team, the company said.
The ISE 13 suite delivers new open standards in line with Xilinx's plug-and-play initiative and shortens design creation times by easing development with Xilinx and third party IP, Xilinx said. New in this release is a configuration option to the AXI interconnect that allows a 50 percent reduction in the interconnect silicon footprint using sparsely connected AXI4 interconnect, the company said.
Also including in ISE 13 is a new documentation navigator, that, according to Xilinx, improves key facets of Xilinx documentation management, including viewing, discovering, searching, and downloading. The Navigator brings Xilinx FPGA device, software, boards and targeted reference design documentation into a single, easy to use environment, the company said. The document manager is available for free through the Xilinx web site.
EDA vendors Synopsys Inc. and Mentor Graphics Corp. also announced support for ISE 13. Synopsys said its Synplify FPGA synthesis and Synphony hierarchical high-level synthesis products support ISE 13, while Mentor said its Precision synthesis tool would also support Xilinx's series 7 FPGAs in conjunction with ISE 13.
ISE 13, immediately available for all ISE Editions and list priced starting at $2,995 for the logic edition, now supports 32- and 64- bit Windows 7, Xilinx said. Customers can download full-featured 30-day evaluation versions at no charge from the Xilinx website.
ISE Design Suite 13 introduces accelerated verification, plug-and-play IP with IP-XACT support and a new team design methodology that shortens design cycles with timing repeatability for multiple engineers working in parallel, according to Xilinx (San Jose, Calif.).
According to Xilinx, ISE 13 also emphasizes speeding the verification process—which now accounts for over half of design cycle time—with a new hardware co-simulation capability and AMBA4 AXI4 bus functional simulation models. Leveraging Xilinx's portfolio of development boards, kits and Xilinx's ISE Simulator, design teams can now accelerate simulation runs that previously would take hours into minutes, according to the company. Through real-time simulation, verification engineers can test implemented blocks of the design while leaving other blocks that are still under development in the simulator accelerating overall verification by up to 100 times faster than native simulation, Xilinx said.
Also new to ISE 13 is a team design methodology, which addresses the challenge of multiple engineers working on a single project by providing a methodology for group of developers to work in parallel, according to Xilinx. Building on the design preservation capability made available in ISE 12, the team design flow provides additional functionality and allows early implementation results on completed portions of the design to be locked down without having to wait for the rest of the design team, the company said.
The ISE 13 suite delivers new open standards in line with Xilinx's plug-and-play initiative and shortens design creation times by easing development with Xilinx and third party IP, Xilinx said. New in this release is a configuration option to the AXI interconnect that allows a 50 percent reduction in the interconnect silicon footprint using sparsely connected AXI4 interconnect, the company said.
Also including in ISE 13 is a new documentation navigator, that, according to Xilinx, improves key facets of Xilinx documentation management, including viewing, discovering, searching, and downloading. The Navigator brings Xilinx FPGA device, software, boards and targeted reference design documentation into a single, easy to use environment, the company said. The document manager is available for free through the Xilinx web site.
EDA vendors Synopsys Inc. and Mentor Graphics Corp. also announced support for ISE 13. Synopsys said its Synplify FPGA synthesis and Synphony hierarchical high-level synthesis products support ISE 13, while Mentor said its Precision synthesis tool would also support Xilinx's series 7 FPGAs in conjunction with ISE 13.
ISE 13, immediately available for all ISE Editions and list priced starting at $2,995 for the logic edition, now supports 32- and 64- bit Windows 7, Xilinx said. Customers can download full-featured 30-day evaluation versions at no charge from the Xilinx website.
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