Open-Silicon updates 'Interlaken' IP core

LONDON – Design house and semiconductor IP provider Open-Silicon Inc. has announced the availability of an enhanced version of its Interlaken controller IP core.

The updated core features configurable mapping between logical and physical SerDes lanes. As Interlaken interfaces routinely target SerDes rates greater than 10-Gbps, custom mapping of the logical and physical SerDes lanes provides flexibility.

The enhanced core also carries forward existing features such as Interlaken-LA, In-Band and Out-of-Band flow control, multiple user-interface options, flexible statistics counters and built-in interrupt structures. This controller is compliant with Interlaken Protocol Definition v 1.2, the Interlaken Look-Aside Protocol Definition v1.1, and the Interlaken Interop Recommendations v1.4.

The Interlaken protocol combines the advantages of the SPI4.2 and XAUI interfaces, Open-Silicon's Interlaken IP can scale from 10-Gbps to over 300-Gbps of bandwidth through the combination of SerDes speed from 3.125-Gbps to 12.5-Gbps and a variable number of SerDes lanes up to 24. This scalability makes Interlaken suitable for network switches, routers and storage equipment.


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