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Mentor claims real-time signoff verification
3/10/2011 1:56 PM EST
SAN FRANCISCO—Mentor Graphics Corp. Thursday (March 10) announced a new capability for its Calibre physical verification platform said to enable signoff-quality physical verification during design creation.
Mentor (Wilsonville, Ore.) said the Calibre RealTime platform provides instantaneous design rule checking (DRC) in the SpringSoft Laker custom IC design and layout solution, using the same Calibre decks as the signoff flow.
The new solution gives designers, for the first time, the full power of Calibre’s signoff engines and qualified decks during design, allowing them to optimize their layouts for performance without sacrificing manufacturing yield, Mentor said.
A version RealTime for the Mentor IC Station custom design environment will be available in June, Mentor said.
The design rule manual for a new technology has grown significantly over the past 10 years to hundreds of pages. Mentor said design teams can no longer rely on their memory and manual checks to avoid design rule violations in their layouts. Design groups working at 32-nm and beyond are reporting a significant increase in the difficulty of converging to a high-quality layout that is completely DRC-clean, according to the company.
"Having the signoff design rule checks in real time, while creating the layout, allows the designer to break the LVS-DRC-LVS loop," said Ted Buchwald, a senior engineer at Mobius Semiconductor, in a statement issued by Mentor. "When a block is LVS-clean, it's DRC-clean and ready for extraction.
"By making Calibre also instantly available in the design creation phase, we can short-circuit the divergence between design tool checking and signoff and make custom designers more productive," said Joseph Sawicki, vice president and general manager of Mentor's Design-to-Silicon division.
Calibre RealTime verification is virtually instantaneous, enabling designers to complete DRC-clean designs in a fraction of the time previously required, according to Mentor.
Mentor (Wilsonville, Ore.) said the Calibre RealTime platform provides instantaneous design rule checking (DRC) in the SpringSoft Laker custom IC design and layout solution, using the same Calibre decks as the signoff flow.
The new solution gives designers, for the first time, the full power of Calibre’s signoff engines and qualified decks during design, allowing them to optimize their layouts for performance without sacrificing manufacturing yield, Mentor said.
A version RealTime for the Mentor IC Station custom design environment will be available in June, Mentor said.
The design rule manual for a new technology has grown significantly over the past 10 years to hundreds of pages. Mentor said design teams can no longer rely on their memory and manual checks to avoid design rule violations in their layouts. Design groups working at 32-nm and beyond are reporting a significant increase in the difficulty of converging to a high-quality layout that is completely DRC-clean, according to the company.
"Having the signoff design rule checks in real time, while creating the layout, allows the designer to break the LVS-DRC-LVS loop," said Ted Buchwald, a senior engineer at Mobius Semiconductor, in a statement issued by Mentor. "When a block is LVS-clean, it's DRC-clean and ready for extraction.
"By making Calibre also instantly available in the design creation phase, we can short-circuit the divergence between design tool checking and signoff and make custom designers more productive," said Joseph Sawicki, vice president and general manager of Mentor's Design-to-Silicon division.
Calibre RealTime verification is virtually instantaneous, enabling designers to complete DRC-clean designs in a fraction of the time previously required, according to Mentor.
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