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resistion

3/22/2011 4:27 AM EDT

Your stacking example uses logic, but for cost-conscious memory, shouldn't there ...

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docdivakar

3/21/2011 6:08 PM EDT

While alternatives to lithography challenges is one value prop for 3D, there is ...

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Analysis: Litho world needs a shrink

Dylan McGrath, Mark Lapedus

3/14/2011 1:13 AM EDT

SAN JOSE, Calif. – For decades, lithography has been the key chip-production technology to scale or shrink a chip.

That still holds true. But at the recent SPIE Advanced Lithography conference here, there were signs that the lithography community- and their customers-literally needed a shrink, the slang term for a psychiatrist.

Anxiety, stress and worry are perhaps some of the conditions to describe lithographers today. Perhaps there are more serious afflictions involved, as the three main next-generation lithography (NGL) candidates-extreme ultraviolet (EUV), maskless and nano-imprint-remain late and delayed. The fourth NGL option, directed self-assembly, is gathering momentum, but it is still in the exploratory stage.

A cure for the blues in lithography remains elusive. Today’s 193-nm immersion lithography continues to extend far beyond what was once possible. At one time, there was a belief that 193-nm immersion would hit the wall at 32-nm, but amazingly, it appears the technology can be extended to the 1x-nm nodes. But to get to those geometries, chip makers must resort to more and more expensive double-patterning steps.   

In contrast, EUV, the leading NGL candidate for chip makers, remains dogged by delays with the power sources, resists and the critical mask and metrology infrastructure. And as a result, EUV continues to slip and is in jeopardy of missing another insertion point, this time, the early stages of the 1x-nm device nodes.  

There is a sense of urgency for EUV among NAND flash vendors, which are leading the charge in scaling. NAND flash vendors pushed 193-nm immersion to the 2x-nm node, and need EUV sooner than later for the development of 1x-nm parts. ''We wanted (EUV) yesterday,’’ said Tuan Pham, director of technology at SanDisk Corp., at SPIE. The duo of SanDisk and Toshiba Corp. have a NAND fab flash venture in Japan.

Asked if he was concerned about the status of EUV, Harry Levinson, senior fellow at Globalfoundries Inc. and manager of strategic lithography at the company, said: ''I get paid to worry.”

Because EUV continues to trail device scaling, one tool maker, ASML Holding NV, has reportedly floated the idea of reducing the EUV wavelength from 13-nm to 6.7-nm as a means to play catch-up with Moore’s Law. What that means is the industry must develop a new and costly EUV tool technology and infrastructure-a concept that sent shivers down the spines of experts in the arena.

In any case, leading-edge chip makers, who are in the EUV camp, are now keeping their options open for the other NGL technologies-such as maskless, nano-imprint and even self-assembly-for future IC production. ''There is so much at stake,’’ said Risto Puhakka, president of VLSI Research Inc. ''If you make the wrong bet, it could be a disaster.’’

There is a silver lining, however. The problems in bringing up EUV and other NGLs have suddenly caused a wave of new spending and job hiring in the industry. Still others think that the NGL effort is a giant boondoggle, which is intended to keep the money flowing to senseless R&D.    

For years, the industry has relied on traditional optical lithography to remain on Moore’s Law. But as far back as the 1970s, there was fear that optical lithography would run out of gas.

At the time, chip makers thought they would need expensive X-ray lithography to scale devices. When optical lithography broke the 1-micron barrier in the 1980s, the technology pushed out the need for X-ray, and eventually, it put the nail in the coffin for X-ray.

Then, in the 1990s, there were once again fears that optical lithography was on its last legs. At that time, there were a multitude of NGL candidates for 65-nm chip production and below: 157-nm wavelength, e-beam, electron projection lithography (EPL), EUV, ion beam, Scalpel scanning e-beam, among others. In the last decade, high-index, nano-imprint, maskless and self-assembly appeared.      

Over time, 157-nm, high-index, EPL, Scalpel and others were dropped. Today, the four remaining contenders are EUV, nano-imprint, maskless and self-assembly.

In the 1990s, there was a major push for EUV, a soft X-ray technology. Intel, Advanced Micro Devices, Motorola and a consortium of national laboratories were developing EUV technology at Lawrence Livermore Labs in Livermore, Calif.

Next: EUV is born




resistion

3/14/2011 5:00 AM EDT

Absence of "cost-savior" sudden improvement EUV and other NGLs has still kept the leading edge players at the leading edge with the help of the ever-increasing wall of costly litho.

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any1

3/14/2011 9:22 AM EDT

The lack of an affordable NGL technology means that the era of "more than Moore" will be thrust upon the vast majority of the semiconductor industry in the forseeable future as scaling slows.

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Frank Rationale

3/14/2011 5:01 PM EDT

I bet EUV would love to switch its remaining challenges with nanoimprint or even maskless. Both have far fewer hurdles to cover - none of which require severe negotiations with Mother Nature.

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bec

3/14/2011 9:34 PM EDT

I completely agree any1. As scaling slows, or as only the 'few' deep pockets can afford it, the rest of the industry will need other options to make faster, better, & cheaper devices. 3D could be one of those affordable options. Monolithic 3D might be a good solution for many products. See http://www.monolithic3d.com/2/post/2011/03/guest-contribution-entanglement-squared-by-zvi-or-bach.html

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resistion

3/14/2011 11:00 PM EDT

3D is probably one of the better options, but is it actually cheaper? It is still cost-additive per layer/plane, isnt' it?

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bec

3/14/2011 11:47 PM EDT

Good question resistion. With it's rich vertical connectivity (vertical interconnect density ~ horizontal interconnect density) and shorter wires, we can remove many of the repeater buffers and as well as make smaller drivers between subcircuits. A logic chip would be 2 layers of 25% the size (50mm2 2D becomes 2x12mm2 in m3D). See one calculation at http://www.monolithic3d.com/why-monolithic-3d.html . Another ref is L. Zhou, et al., “Implementing a 2-Gbs 1024-bit ½-rate low-density parity-check code decoder in three-dimensional integrated circuits”, Proc. ICCD, 2007. It about one node of scaling.

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resistion

3/15/2011 5:46 AM EDT

Thanks for the info and references!

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resistion

3/22/2011 4:27 AM EDT

Your stacking example uses logic, but for cost-conscious memory, shouldn't there be concern?

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docdivakar

3/21/2011 6:08 PM EDT

While alternatives to lithography challenges is one value prop for 3D, there is also the issue of package connectivity that will force one to adopt stacking chips. The intra-processor communication (IPC) and/or inter chip to chip communication pipelines at higher data rates (40/100Gig) using differential signaling is already congesting the server / switch mother boards. 3D will be a good answer as long as thermal and power management issues are addressed.

Dr. MP Divakar

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