datasheets.com EBN.com EDN.com EETimes.com Embedded.com PlanetAnalog.com TechOnline.com  
Events
UBM Tech
UBM Tech

News & Analysis

Comment


resistion

3/22/2011 4:27 AM EDT

Your stacking example uses logic, but for cost-conscious memory, shouldn't there ...

More...



docdivakar

3/21/2011 6:08 PM EDT

While alternatives to lithography challenges is one value prop for 3D, there is ...

More...

Analysis: Litho world needs a shrink

Dylan McGrath, Mark Lapedus

3/14/2011 1:13 AM EDT

EUV is born
EUV constitutes a major departure from today's tools. It uses a 13.5-nm wavelength, and the processing steps take place in a vacuum chamber. The optical elements are basically defect-free mirrors that reflect light by means of interlayer interference.

At one time, EUV was supposed to be ready for production at the 65-nm node, but the technology remains delayed. And the cost-of-owership (COO) equation remains a concern, as an EUV ''photo-cluster’’ sells for $120 million today, compared to $70 million for today’s optical ''photo-cluster,” according to Globalfoundries’ Levinson.

ASML, Canon Inc., and Nikon Corp. were the three prospective EUV scanner makers. Recently, Canon has dropped out of the leading-edge lithography race.

The two remaining vendors, ASML and Nikon, have different strategies. ASML is pushing hard to bring EUV to the 22-nm node, but Nikon believes that the technology will not be ready until the 16- or 11-nm nodes. ''Nikon anticipates a delay in EUV ecosystem readiness,’’ said Yuichi Shibasaki, general manager of the Next Generation Development Department for Nikon, at SPIE.

Nikon has also been developing an EUV tool, dubbed the EUV1, a production system that is reportedly expected to ship in 2012 or so.      

ASML’s strategy is clear. Like its 193-nm immersion strategy, the company is shipping pre-production EUV tools to customers early-and before Nikon. Customers gain experience on ASML’s EUV tools, thereby hoping to lock Nikon out of the market.  

So far, ASML has shipped two alpha EUV tools, including one to Albany Nanotech and another to IMEC. ASML has recently shipped its first standalone, pre-production EUV tool-the NXE:3100-to Samsung Electronics Co. Ltd.  

ASML has just shipped another one to IMEC. In total, the company has six orders for NXE:3100. The company has several orders for the NXE:3300, the first, production-worthy machine that is expected to ship in the first half of next year.

The NXE:3100 is said to have a resolution of 27-nm, a numerical aperture (NA) of 0.25, a field size of 26-nm, an overlay of 4-nm and flare at less than 5 percent. The tool sells for nearly $100 million a unit.

The stated goal of the tool is to have an overall throughput of 60 wafers an hour by year’s end. But right now, the tool has a throughput of only 5 wafers an hour. EUV tools need some 200 Watts of power to process 100 to 150 wafers an hour. At present, the current EUV tool from ASML is only running at about 10 Watts.

Analysts believe ASML has done a commendable job in getting the EUV tool ready. Now, the company-and EUV customers-are waiting on the power sources, which are being developed by several third parties.

ASML appears to be patient with the power source vendors despite the issues. ''We have three vendors working full throttle,’’ said Martin van den Brink, executive vice president and chief product and technology officer for ASML.

ASML has two power source suppliers for the NXE:3100 tool: Cymer Inc. and Ushio Inc. Cymer has devised a power source based on laser-produced plasma (LPP) technology.  At present, Cymer’s LPP source is running at a sustained power of 11 Watts, according to ASML.

Rival Ushio is developing a power source based on electric discharge technology. At present, the source has demonstrated 12 watts of power, according to ASML. Another vendor, Gigaphoton Inc., has demonstrated 20 Watts of power.

''On the plus side, Cymer has already shipped four EUV sources to customers and preparing to ship a fifth one, with initial feedback from Samsung (who began initial wafer patterning in December 2010) being mixed–the patterning is good, but throughput is poor,’’ said C.J. Muse, an analyst with Barclays Capital, in a report.




resistion

3/14/2011 5:00 AM EDT

Absence of "cost-savior" sudden improvement EUV and other NGLs has still kept the leading edge players at the leading edge with the help of the ever-increasing wall of costly litho.

Sign in to Reply



any1

3/14/2011 9:22 AM EDT

The lack of an affordable NGL technology means that the era of "more than Moore" will be thrust upon the vast majority of the semiconductor industry in the forseeable future as scaling slows.

Sign in to Reply



Frank Rationale

3/14/2011 5:01 PM EDT

I bet EUV would love to switch its remaining challenges with nanoimprint or even maskless. Both have far fewer hurdles to cover - none of which require severe negotiations with Mother Nature.

Sign in to Reply



bec

3/14/2011 9:34 PM EDT

I completely agree any1. As scaling slows, or as only the 'few' deep pockets can afford it, the rest of the industry will need other options to make faster, better, & cheaper devices. 3D could be one of those affordable options. Monolithic 3D might be a good solution for many products. See http://www.monolithic3d.com/2/post/2011/03/guest-contribution-entanglement-squared-by-zvi-or-bach.html

Sign in to Reply



resistion

3/14/2011 11:00 PM EDT

3D is probably one of the better options, but is it actually cheaper? It is still cost-additive per layer/plane, isnt' it?

Sign in to Reply



bec

3/14/2011 11:47 PM EDT

Good question resistion. With it's rich vertical connectivity (vertical interconnect density ~ horizontal interconnect density) and shorter wires, we can remove many of the repeater buffers and as well as make smaller drivers between subcircuits. A logic chip would be 2 layers of 25% the size (50mm2 2D becomes 2x12mm2 in m3D). See one calculation at http://www.monolithic3d.com/why-monolithic-3d.html . Another ref is L. Zhou, et al., “Implementing a 2-Gbs 1024-bit ½-rate low-density parity-check code decoder in three-dimensional integrated circuits”, Proc. ICCD, 2007. It about one node of scaling.

Sign in to Reply



resistion

3/15/2011 5:46 AM EDT

Thanks for the info and references!

Sign in to Reply



resistion

3/22/2011 4:27 AM EDT

Your stacking example uses logic, but for cost-conscious memory, shouldn't there be concern?

Sign in to Reply



docdivakar

3/21/2011 6:08 PM EDT

While alternatives to lithography challenges is one value prop for 3D, there is also the issue of package connectivity that will force one to adopt stacking chips. The intra-processor communication (IPC) and/or inter chip to chip communication pipelines at higher data rates (40/100Gig) using differential signaling is already congesting the server / switch mother boards. 3D will be a good answer as long as thermal and power management issues are addressed.

Dr. MP Divakar

Sign in to Reply



Please sign in to post comment

Navigate to related information

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)