LONDON – Non-volatile memory bits can be made by applying phase-change material to previously created nanometer-scale gaps in carbon nanotube filamentary conductors, according to a paper published by researchers at the University of Illinois, Urbana-Champaign, Illinois.
The configuration achieves programming currents as low as 0.5 microamps for set and 5 microamps for reset operations, two orders of magnitude lower than state-of-the-art devices, the authors claim in their ScienceExpress
paper, published March 10.
The researchers, led by Professor Eric Pop of University of Illinois, grew single-wall and multi-wall carbon nanotubes with diameters of between 1 and 6 nanometers and then used electrical breakdown, e-beam writing or an atomic force microscope to form a gap of less than 100 nanometers in each wire. The devices than received a sputtered layer of germanium-antimony-tellurium (GST) so that the gaps in the CNTs are filled with the phase-change material. Although amorphous GST is laid down over the entire device, the switching occurs only in the nanogap of the CNT, which is the location of highest electric field and heating effect.
The authors claim their results address the scaling of both the size and power reduction that is possible with programmable PCM bits. The paper reports on reversible switching with programming currents between 1 and 8 microamps, two orders of magnitude lower than state-of-the-art PCM devices. The PCM material switches between an off resistance of 50-megaohm to an on resistance of 2-Mohm but which can be as low 500-kohm, depending on sample preparation.
The authors report hundreds of switching cycles. Conventional PCM devices have been reported at more than 1 million cycles endurance.
The creation of nano-debris in the formation of the CNT gaps does not appear to be a problem, according to Professor Pop. "
nanogaps are formed by an oxidation process, so it is possible that the C atoms
combine with O atoms forming gas (CO or CO2), not solid debris. Regardless,
debris does not seem to be a problem since the nanotubes show a “clean cut”
after imaging with atomic force microscopy (AFM)," Professor said in email correspondence with EE Times
Professor Pop and his team only worked with individual devices. "That being said, I think the integration could be pretty high if the nanotubes could be closely spaced. Perhaps one could fit even up to 100 parallel nanotubes side-by-side (~10 nm spacing) and the memory bits could still work without cross-talk. This is just an educated guess based on some calculations we’ve done, not something that we have achieved in practice, yet, he said.
The authors go on to suggest that 5-nm GST bits in a CNT gap could operate at 0.5-V and less than 1 microamp, such that nanosecond switching times would result in sub femtojoule-per-bit energy consumption. There is also the option to use GeSb which has a lower switching threshold. The authors claim the results are "encouraging for ultra-low power electronics and memory based on programmable PCM with nanoscale carbon interconnects."
Professor Pop agreed that blowing billions of CNTs electrically serially would be too time consuming and that doing it one pass would consume too much power. "Yes,
we’ve considered this, but we don’t think this is necessarily the way to go for
a commercial application," said Professor Pop. "Commercially, nanogaps would probably be made through some large-scale etching
process, in large CNT arrays," he added.
However, the paper does not address
the introduction of additional manufacturing complexity, so the
development is a long way from being proven as a useful commercial
Micron Technologies Inc. and Samsung Electronics Co. Ltd. are the two companies most active in commercial phase-change memory. Both have 1-Gbit designs but neither company is boasting of high volume sales into commercial designs and concerns have been raised over the ability of conventional PCM-on-silicon memories to scale and compete with flash memory which is already at higher than 1-Gbit capacity implemented on processes with finer minimum dimensions.
Related links and articles:
Samsung CEO: Headwinds hinder PRAM
Update: PCM found in handset
CTO confirms IBM's PCM expectations
A series of articles on PCM by Ron Neale published in EE Times Memory Design Line:
PCM Progress: Temperatures rise and constituents on the move
PCM The Myth of Scalability Part 3- Is WAL-PCM the salvation?
PCM Scalability:The Myth (Part 2)
PCM scalability--Myth or realistic device projection (Part 1)