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NimrodO0l1
Not sure I understand the reduction in engineers either, but you should get ...
changjm
We are equipment vendors to do our best to maintain the equipment and improve ...
Why is TSMC moving into 450-mm?
Mark Lapedus
4/6/2011 3:00 PM EDT
SAN JOSE, Calif. – During the TSMC 2011 Technology Symposium here on Tuesday (April 5), Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) provided more details about its efforts in the 450-mm arena.
As reported, TSMC is moving full speed ahead into the 450-mm fab era. The move is intended to reduce production costs and stay one step ahead of its rivals, such as Globalfoundries, Samsung, UMC and others.
There is another motivation for TSMC’s move into 450-mm. In the 450-mm era, the company will require ''fewer engineers’’ over time, thereby reducing costs, said Shang-Yi Chiang, senior vice president of R&D at TSMC.
In fact, TSMC will need 7,000 fewer engineers over a 10-year period when it enters into the 450-mm era, he told EE Times.
There are two factors at play in 450-mm. First, TSMC believes it will become more and more difficult to attract ''good engineers’’ over time, he said.
Second, TSMC will ultimately require fewer 450-mm fabs to meet customer demand in the future. The next-generation wafer size is projected to boost overall chip productivity by 1.8 times or more, as compared to 300-mm.
Fewer fabs equates to less engineers. On the other hand, TSMC is expected to increase its R&D and capital spending, especially as it continues to march down the process technology curve.
450-mm fabs, for example, will run $10 billion or so. And tool costs are expected to soar in the 450-mm era.
As expected, TSMC’s intercept point for 450-mm fabs will be at the 20-nm node, Chiang said. Initially, TSMC hopes to install a 450-mm pilot line in Fab 12 in Hsinchu, Taiwan. The line will process wafers at the 20-nm node. It hopes to get the pilot line up and running by 2013 to 2014.
At that time, TSMC’s 300-mm fabs will also process wafers based on 20-nm technology. In fact, most of TSMC’s initial 20-nm output will center around its 300-mm fabs, he said.
Then, TSMC plans to bring up its first 450-mm production fab in Taichung, Taiwan. The Taichung plant is called Fab 15. Production is slated for 2015 to 2016.
Initially, that 450-mm fab may ramp up 20-nm wafer production, with plans to move to 14-nm. At 14-nm, TSMC plans to make a switch in transistor structures.
At the 20-nm node and above, TSMC will continue to use traditional planar transistors based on bulk CMOS. At 14-nm, the company plans to make the switch from bulk CMOS to FinFET structures, he said.
So in the future, the company will produce 14-nm FinFETs in production in Fab 15.
As reported, TSMC is moving full speed ahead into the 450-mm fab era. The move is intended to reduce production costs and stay one step ahead of its rivals, such as Globalfoundries, Samsung, UMC and others.
There is another motivation for TSMC’s move into 450-mm. In the 450-mm era, the company will require ''fewer engineers’’ over time, thereby reducing costs, said Shang-Yi Chiang, senior vice president of R&D at TSMC.
In fact, TSMC will need 7,000 fewer engineers over a 10-year period when it enters into the 450-mm era, he told EE Times.
There are two factors at play in 450-mm. First, TSMC believes it will become more and more difficult to attract ''good engineers’’ over time, he said.
Second, TSMC will ultimately require fewer 450-mm fabs to meet customer demand in the future. The next-generation wafer size is projected to boost overall chip productivity by 1.8 times or more, as compared to 300-mm.
Fewer fabs equates to less engineers. On the other hand, TSMC is expected to increase its R&D and capital spending, especially as it continues to march down the process technology curve.
450-mm fabs, for example, will run $10 billion or so. And tool costs are expected to soar in the 450-mm era.
As expected, TSMC’s intercept point for 450-mm fabs will be at the 20-nm node, Chiang said. Initially, TSMC hopes to install a 450-mm pilot line in Fab 12 in Hsinchu, Taiwan. The line will process wafers at the 20-nm node. It hopes to get the pilot line up and running by 2013 to 2014.
At that time, TSMC’s 300-mm fabs will also process wafers based on 20-nm technology. In fact, most of TSMC’s initial 20-nm output will center around its 300-mm fabs, he said.
Then, TSMC plans to bring up its first 450-mm production fab in Taichung, Taiwan. The Taichung plant is called Fab 15. Production is slated for 2015 to 2016.
Initially, that 450-mm fab may ramp up 20-nm wafer production, with plans to move to 14-nm. At 14-nm, TSMC plans to make a switch in transistor structures.
At the 20-nm node and above, TSMC will continue to use traditional planar transistors based on bulk CMOS. At 14-nm, the company plans to make the switch from bulk CMOS to FinFET structures, he said.
So in the future, the company will produce 14-nm FinFETs in production in Fab 15.
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resistion
4/6/2011 4:22 PM EDT
Fewer 450 mm fabs (half compared to 300 mm say) could be a hazard in terms of contingencies.
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walken1
4/6/2011 4:50 PM EDT
I'm curious as to why TSMC feels that it will become more and more difficult to attract good engineers over time. If anything, I would think that the industry consolidation and job displacement currently underway is leading to a greater surplus of engineering talent. Or perhaps is TSMC taking the long view and seeing this trend driving fewer engineering students to enter the semiconductor field in the next wave/generation? Interested in any thoughts on the matter.
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mark.lapedus
4/6/2011 5:04 PM EDT
TSMC believes fewer (good) engineers will enter the IC field.....
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RobDinsmore
4/6/2011 6:44 PM EDT
That's a good point Mark. I recently entered the field myself after completing my Physics Ph.D. in '08. Maybe it was just timing, but 2 different senior engineers that I interviewed with both essentially asked why I wanted to enter a dying industry.
The fab engineer job also can produce a very poor quality of life. In my experience, the really good ones leave for more fulfilling careers with greater upward mobility. Well at least that's what I did, albeit I am still working on process R&D.
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Warren
4/6/2011 6:47 PM EDT
I don't see this putting TSMC ahead of Samsung.
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changjm
10/30/2011 4:10 AM EDT
We are equipment vendors to do our best to maintain the equipment and improve the process for TSMC.
I think fewer engineers or operators doesn't represent the fewer people working in the fab because it will still need more professional vendors to maintain the complicated tools or improve the process in the fab because new generation machines are more complicated and expensive.
Of course many professional people inside the fab without any contingencies.
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goafrit
4/7/2011 9:00 AM EDT
They must because Intel and others are moving there. That is the future but it will not be easy. It will not be.
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iniewski
4/7/2011 1:05 PM EDT
Rob, congrats, you have just entered dying industry!;-)...Kris
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chipmonk
4/7/2011 1:38 PM EDT
At the Symposium TSMC said that over the last 5 years they have boosted the number of process R&D engineers by 3x !!
Perhaps they have finally run out of Chinese speaking Process Engr.s trained in the US and this claim of requiring fewer Engr.s as an argument for going to 450 mm is plain wishful thinking.
Maintaining process uniformity over a larger wafer is never a trivial challenge and transition from 300 to 450 mm too will also require a lot of engineering resources - even if modeling etc. will help a lot more in chamber design etc.
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docdivakar
4/7/2011 2:40 PM EDT
450mm makes sense to go to commoditized products like memory and cheap logic but creates one hell of a problem in wafer handling, especially when there is Wafer to Wafer stacking involved. But then again, TSMC said they are going to expand their packaging & test efforts, may be they are on to something that gives them an edge in this 450mm business overall.
MP Divakar
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NimrodO0l1
6/12/2012 4:07 PM EDT
Not sure I understand the reduction in engineers either, but you should get twice the parts per wafer without a shrink due to doubling of area.
If you do a shrink, you might get twice again.
If the number of process steps is about constant, then you expect 4x the parts per operator hour.
Intel and others have estimated a 30%+ in cost per chip. It would appear that much of it comes from reduced human hours per chip.
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