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ManasK.RayChaudhuri
Let us wait and watch the reactions of other companies.
ManasK.RayChaudhuri
It is definitely not crap.Await the results.
A5: All Apple, part mystery
Paul Boldt and Don Scansen
4/13/2011 12:01 AM EDT
How Apple did on the A5
There were two pieces of information to come out of the early reverse engineering from the big RE houses. First, the A5 die is dramatically larger than the A4. Both UBM Techinsights and Chipworks found the A5 die to be 12.1 mm x 10.1 mm, giving a die size of 122 mm2. This compares to 53 mm2 for the A4. The die size of the A5 is therefore 2.3 x larger than the A4.
Let's look closer at the A4 and A5 floorplans and consider what might be behind such a dramatic increase in die size for the A5. For this comparison we look to the floorplans published by Chipworks. The two ARM cores of the A5 combine to consume approximately 14 percent of the total die area. This is the roughly the same percentage as the single ARM core in the A4.
What about the GPU? The published floorplan of the A4 does not specifically identify it. However, if you assume it is a moderate size block with a fair amount of cache there is logic core 4, which is the largest outside the CPU and logic core 5. It is also noted that there are numerous blocks of approximately the same size as logic core 5. For the sake of the discussion let's assume core 4 is the GPU. In terms of absolute areas, If the CPU and GPU areas are added and the total subtracted from the overall die size there are 41 mm2 left for other digital blocks, analog and I/O for the A4.
Now to the A5
We are not aware of any published floorplan, including the one cited above, that explicitly identifies the GPUs, so some assumptions will be made. There are three sets of two identical blocks clustered together. Two of these are labeled as the ARM cores and four are labeled as "Processor Data Path." There are no two other blocks that appear the same. For a dual core system one would anticipate some sort of arbitration has to occur between them, agreeing with the labeling. However in the absence of two other blocks that are the same, it is believed that the two GPUs are within these blocks, or area. In the end, again for the sake of argument, these six blocks representing CPU+GPU+arbitration consume approximately 40 percent or 47 mm2 on the A5 die, leaving 75 mm2 for other stuff.
Infrared backside die image of Apple's A4 applications processor with single ARM core indicated.
Die size and architecture comparison of larger dual core Apple A5 applications processor.
Source: Chipworks.
The second piece of early information was that both the A4 and A5 are manufactured in Samsung's 45-nm process. This point makes a comparison of the published A4 and A5 floorplans that much easier. Because the two dies are fabbed with the same process node the analog blocks came out looking pretty much the same.
Thus, one can readily identify the Wi-Fi and audio blocks in the A4 die photo as they are labeled and appear the same, apart for minor layout differences, on the A5. Finally, for the sake of argument it is assumed that the IP cores on the A4 are also present on the A5, and any differences in area consumed for I/O and basic IP cores are minor in the overall die area. One then arrives at 34 mm2, or 64% of the total A4 die size, in additional real estate for digital logic on the A5. While the measurements for the above numbers contain some assumptions, they highlight the scale of the differences.
The somewhat simplified area analysis indicates that there is more to the increased die area than just the upgraded and expanded CPU+GPU and the arbitration circuitry. One can arrive at the same conclusion by simply counting the blocks. There are nine digital blocks in addition to the CPU+GPU on the A4. This number increases to 12 for the A5. It is unclear whether we see the same digital blocks on the A5 as we did on the A4. There will likely be some of the same IP cores on the two die. However, by comparing memory array layout in various blocks it is apparent that the layout is different. Of particular note is logic core 6 of the A4, which appears to be a sea of gates with no apparent memory. There is no similar block on the A5. If we combine this observation with the increased number of blocks one readily concludes that there is a lot more going on in the A5 than the switch to a dual core CPU and GPU.
Now it's time to put on our thinking caps. If you were Apple what would your strategy be? We do know there is quite a bit of real estate on the A5 beyond the CPU+GPU+arbitration, and the necessary IP blocks for memory control, I/O etc. So what to do with this extra real estate.
Next: Let's look back again
There were two pieces of information to come out of the early reverse engineering from the big RE houses. First, the A5 die is dramatically larger than the A4. Both UBM Techinsights and Chipworks found the A5 die to be 12.1 mm x 10.1 mm, giving a die size of 122 mm2. This compares to 53 mm2 for the A4. The die size of the A5 is therefore 2.3 x larger than the A4.
Let's look closer at the A4 and A5 floorplans and consider what might be behind such a dramatic increase in die size for the A5. For this comparison we look to the floorplans published by Chipworks. The two ARM cores of the A5 combine to consume approximately 14 percent of the total die area. This is the roughly the same percentage as the single ARM core in the A4.
What about the GPU? The published floorplan of the A4 does not specifically identify it. However, if you assume it is a moderate size block with a fair amount of cache there is logic core 4, which is the largest outside the CPU and logic core 5. It is also noted that there are numerous blocks of approximately the same size as logic core 5. For the sake of the discussion let's assume core 4 is the GPU. In terms of absolute areas, If the CPU and GPU areas are added and the total subtracted from the overall die size there are 41 mm2 left for other digital blocks, analog and I/O for the A4.
Now to the A5
We are not aware of any published floorplan, including the one cited above, that explicitly identifies the GPUs, so some assumptions will be made. There are three sets of two identical blocks clustered together. Two of these are labeled as the ARM cores and four are labeled as "Processor Data Path." There are no two other blocks that appear the same. For a dual core system one would anticipate some sort of arbitration has to occur between them, agreeing with the labeling. However in the absence of two other blocks that are the same, it is believed that the two GPUs are within these blocks, or area. In the end, again for the sake of argument, these six blocks representing CPU+GPU+arbitration consume approximately 40 percent or 47 mm2 on the A5 die, leaving 75 mm2 for other stuff.
Die size and architecture comparison between
larger dual core Apple A5 APU and the first
generation A4
larger dual core Apple A5 APU and the first
generation A4
Infrared backside die image of Apple's A4 applications processor with single ARM core indicated.
Die size and architecture comparison of larger dual core Apple A5 applications processor.
Source: Chipworks.
The second piece of early information was that both the A4 and A5 are manufactured in Samsung's 45-nm process. This point makes a comparison of the published A4 and A5 floorplans that much easier. Because the two dies are fabbed with the same process node the analog blocks came out looking pretty much the same.
Thus, one can readily identify the Wi-Fi and audio blocks in the A4 die photo as they are labeled and appear the same, apart for minor layout differences, on the A5. Finally, for the sake of argument it is assumed that the IP cores on the A4 are also present on the A5, and any differences in area consumed for I/O and basic IP cores are minor in the overall die area. One then arrives at 34 mm2, or 64% of the total A4 die size, in additional real estate for digital logic on the A5. While the measurements for the above numbers contain some assumptions, they highlight the scale of the differences.
The somewhat simplified area analysis indicates that there is more to the increased die area than just the upgraded and expanded CPU+GPU and the arbitration circuitry. One can arrive at the same conclusion by simply counting the blocks. There are nine digital blocks in addition to the CPU+GPU on the A4. This number increases to 12 for the A5. It is unclear whether we see the same digital blocks on the A5 as we did on the A4. There will likely be some of the same IP cores on the two die. However, by comparing memory array layout in various blocks it is apparent that the layout is different. Of particular note is logic core 6 of the A4, which appears to be a sea of gates with no apparent memory. There is no similar block on the A5. If we combine this observation with the increased number of blocks one readily concludes that there is a lot more going on in the A5 than the switch to a dual core CPU and GPU.
Now it's time to put on our thinking caps. If you were Apple what would your strategy be? We do know there is quite a bit of real estate on the A5 beyond the CPU+GPU+arbitration, and the necessary IP blocks for memory control, I/O etc. So what to do with this extra real estate.
Next: Let's look back again
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hm
4/13/2011 12:21 PM EDT
Very good article. A5 is wonderful design. I wish it is available for general embeeded product design! However, it is Apple's final product design and marketing that takes A5 further as compared to other equally good designed SoC.
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luting
4/14/2011 1:23 AM EDT
Could you afford it?
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ManasK.RayChaudhuri
4/21/2011 9:40 PM EDT
Agreed,but one has to consider the price factor.
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elctrnx_lyf
4/13/2011 12:55 PM EDT
A5 and the Apple definitely are tightly coupled to provide best performance to the consumers. Apple has done things differently and they continue to do so!!!
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selinz
4/13/2011 2:01 PM EDT
Interesting article. I'd like to see the AB comparison between Samsung's own CPU for their Galaxy II devices...
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Singh_Y
4/13/2011 2:06 PM EDT
All things considered, Apple has done a great job with the A5 processor platform; However longer term Apple will need to make a decision from a competitive standpoint:
* Should apple continue to use Samsung Foundry at 45 nm process node ?
* Note Samsung is a competitor to Apple in the tablet and phone space
* If Apple could partner with Intel to create a low power , high performance multicore SOC at 28 nm it may be a better option strategically for the next 5 years and a win win for both Intel and Apple
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Moshe.Frankel
4/13/2011 2:18 PM EDT
For Microsoft, Intel, Nokia, Motorola and even Dell and TI it is probably too late. May be even for Google. Nokia should have done it with Symbian, Intel even both an OS,but they all have too much to loose from such a jump in efficiency. only Apple runs a business model that allows it to benefit from what benefit its customers (single source, integration, efficiency). It was a multibillion dollars decision that other with even more money should have made but only apple did. And it is only a question of time until they move to Intels and TI's territory with semiconductor technology they are investing in. Teh already taking a significant share limiting growth of those companies. The article closing words say it all: "Apple likely plans to venture further down the road of custom circuit design. Going beyond the need to remain generic and flexible to accommodate the broadest possible OS market might produce revolutionary hardware-software platforms. "
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Frank Eory
4/13/2011 3:42 PM EDT
Very interesting article, with some well thought-out speculations. In the end, the authors leave 34 mm2 of die area as a mystery. In 45 nm, this represents an enormous amount of logic. Is it possible there are IP blocks in there -- Apple's own, or licensed -- that have not yet been exploited by existing Apple products?
It was a relatively short time, basically a year, between A4 and A5 production readiness. I have a feeling the A5 has much longer legs than the A4 did, and we will not see an A6 next year...but probably in 2013.
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Paul Boldt
4/15/2011 11:53 AM EDT
When the A4 came out there was speculation that it would not support cameras because they were not included in iPad. Then iPhone 4 had two cameras and an A4. While not touching on this thread in the article I suspect the same. There is likely an "upgrade cycle" lurking in there somewhere.
Paul
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EdKorczynski
4/13/2011 6:59 PM EDT
If rumors serve...then after the A5 is ported to the TSMC CLN28HPL process the final die size will be closer to the A4. Then, a further tweak to the CLN28HPM process early in 2012 would presumably provide another performance boost without a re-design. If this plays out (seems like an obvious move, really) then the A5 will be the "low power, high performance multicore SOC at 28 nm" that will remain highly competitive for the next few years. Apple can put more resources into software, and clouds, and brick'n'mortar...and just use Samsung as a 2nd-source for Flash memory.
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GREAT-Terry
4/15/2011 3:09 AM EDT
Good article. Apple is really doing something differently. If the special logic blocks are really something that helps performance in whatever sense, I believe Apple will still lead the market and will lead for long time. Google seems haven't started such a hardware+software integration so it may not be able to catch up. Very anxious to see what the situation can be after 2 years.
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SZA
4/19/2011 3:13 PM EDT
Agreed. With both A4 and A5 on same node and A5 much larger than A4 while iPad still maintaining similar battery life. It certainly seems Apple has exploited clever hardware+software exploitation. It is still relatively hard for rivals to do that in current form (perhaps future close partnerships arise for Android+Samsung, Microsoft+Nokia :)).
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ManasK.RayChaudhuri
4/21/2011 9:47 PM EDT
Let us wait and watch the reactions of other companies.
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ArekZ
4/15/2011 4:12 AM EDT
I wonder if this article is sponsored by Apple. A5 seems to be glorified a lot here but I cannot see anything special in it, except it coming from Apple. Like many other ARM customers, Apple put together a few IP cores in an SoC and the chip does what they wanted, like for other customers.
This article compares A5 only to A4 hence does not really show to the readers the position of A5 in the global market.
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junko.yoshida
4/15/2011 6:27 AM EDT
ArekZ, I would like to make it crystacl clear that this article was NOT sponsored by Apple. I am the editor in chief of EE Times, and I know that it is not the case.
That said, the reason why we are running this article is because Apple has kept mum on their SoC strategy.
They have said very little about what's inside their A4 or A5 processors. The two engineers who contributed this article have done a great job in making "educated guesses" on what Apple might have done to A5, unlocking a few mysteries.
The article also gives us a glimpse of what might be Apple's future SoC strategy.
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Paul Boldt
4/15/2011 11:23 AM EDT
As one of the authors I just want to re-iterate that the article was not sponsored by Apple.
To go back a bit, both the A4 and A5 articles were inspired by Apple's big push into semi. design. This has the possibility to alter landscape.
Since the initial de-capping of the A5 there has been lots of discussion about its die size and if they could have done better. So we were curious and took a look.
Thanks for all of the positive comments.
Paul
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jpnKevin
4/18/2011 3:59 PM EDT
Apple becoming involved in semi-design to higher degree will certainly give them flexibility and may result in an ongoing strategic advantage.
A lot more understanding could have added in the article by comparing it to other ARM Cortex A9 processors on 45nm silicon like OMAP4;
http://focus.ti.com/lit/ml/swpt034b/swpt034b.pdf
Just looking at the block diagram and comparing it to A5 would tell you alot.
You could have discussed differences in size between PowerVR SGX543MP2 in A5 and PowerVR SGX540 in OMAP4;
http://www.anandtech.com/show/4216/apple-ipad-2-gpu-performance-explored-powervr-sgx543mp2-benchmarked
http://en.wikipedia.org/wiki/PowerVR
Even ARM's site itself provides info on example die sizes with different process for development kit chips that give some insight on what to expect.
Cortex A8 supported optional upto 1MB of L2 Cache while A9 supports upto 8MB for example.
Here is an interesting quote;
"A final mobile constraint that must be addressed is balancing the need to minimize die size, but providing large enough memory cache to keep multiple cores from being stalled. If a single core device requires
N amount of cache, up to 4*N cache may be required to achieve good performance in a multicore device.
Other memory design issues include data coherence and system memory consistency, to ensure processors
all have access to the current data at the correct time"
See Page 3;
http://focus.ti.com/pdfs/wtbu/smp_wp_swpy022.pdf
Some more general information from other chip makers of ARM designs would have provided more insight.
Sure there are lots of different IP blocks to choose from and it is important to have designer level understanding to make right choices.
But Apple has nothing to gain making IP choices or custom development public public it is not selling chips. Apple can also benefit from the "magic" of people imagining they are doing much more than they actually are.
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ManasK.RayChaudhuri
4/21/2011 9:43 PM EDT
I would eagerly await a detailed writeup on the subject in order to evaluate properly.
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danny1024
4/15/2011 2:01 PM EDT
What a way to squander the PA-SEMI acquisition (their lead design team has almost entirely jumped ship)and the their PA6T architecture. Rather than unify their entire product range under a single, modern ISA (PowerPC) Apple elected to fragment it with ARM, PowerPC and x86. And to add insult to injury, ARM's Neon SIMD ISA is just woeful compared to VMX or even SSE.
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Singh_Y
4/15/2011 6:27 PM EDT
It would be good to compare A5 to the other Top 3 SOCs; Has EE times ever done a disection of the Atom Processor ? Why would Apple tout the A5 ? An Ideas for future article:
Can the A5 architecture be implemented in a 28 nm FPGA [Altera, Xilinx, Archonix] with similar performance and cost ?
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Stephen.Sliva
4/16/2011 9:04 PM EDT
My guess is that facetime is going to get REALLY fancy. You're looking at multi-way videoconferencing. One-on-one is soooo 2010. All that extra logic is just more GPU-like crap.
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ManasK.RayChaudhuri
4/21/2011 9:45 PM EDT
It is definitely not crap.Await the results.
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