Bandwidth driving technology
Broad changes are expected on the technology front. The previous-generation mobile DRAMs were based on low-power synchronous DRAM technology, and, more recently, LPDDR1. LPDDR1 mobile DRAMs are 1.8-V, 200-MHz parts, enabling 400-Mbyte/s throughput.
Now that LPDDR1 is hitting the performance wall, vendors are ramping up to provide LPDDR2-based devices, which are 1.2-V parts said to reduce power consumption by more than 50 percent. LPDDR2 cuts power by using such techniques as partial array self-refresh.
LPDDR2 runs from 100 to 533 MHz, resulting in data transfer rates from 200 to 1,066 Mbytes/s. Up to four devices can be housed in a package-on-package, resulting in a total data transfer rate of 8.5 Gbytes/s.
Just as vendors are pushing LPDDR2 devices into the channel, Micron Technology Inc. is leading the charge toward LPDDR3, which is said to operate at 800 MHz, or 1.6 Gbytes/s. With four devices, LPDDR3 has a peak throughput of 12.8 Gbytes/s, said Dan Skinner, director of mobile DRAM architecture for Micron.
LPDDR2 will satisfy most mobile system requirements, but in the near term, the “top 10 percent of [high-end systems] will need” LPDDR3, said Skinner, who chairs Jedec’s LPDDR3 task group. A final draft specification for LPDDR3 will be completed by year’s end.
Rival Samsung is lukewarm on LPDRR3; LPDDR2 has long legs and will be the “memory of choice” at least until 2012, said Samsung’s Deen.
Samsung is now shipping 533-MHz, 4-Gbit mobile DRAMs based on LPDDR2 and 30-nanometer-class technologies. The new devices will enable lighter mobile products with a longer battery life, Deen said.
Previously, four 2-Gbit LPDDR2 chips had to be stacked to create a 1-Gbyte package. Stacking only two 4-Gbit LPDDR2 devices will achieve the same 1-Gbyte density, while reducing the package height by 20 percent and cutting power consumption by 25 percent, according to Deen.
Beyond LPDDR2, Samsung has announced support for SPMT and wide I/O. Wide I/O operates at lower frequencies to reduce power. Traditional DRAM has up to 32 data lanes. In contrast, wide I/O DRAM is a four-channel, 128-lane technology, which enables a total of 512 I/Os and a total bandwidth of up to 12 Gbytes/s, according to supporters of the technology.
By 2013, vendors hope to roll out robust wide-I/O DRAMs. In the distant future, vendors believe they can stack multiple wide-I/O memories using through-silicon via 3-D stacking technology, but for now TSV remains hampered by high implementation costs and scant EDA tool support.
“TSV is not ready for prime time,” said SPMT’s Venable, while LPDDR2 is running out of steam, and LPDDR3 is a “stopgap” technology that is faster but will consume more power.
SPMT claims it has the right solution, although it remains unproven. Last year, SPMT scrapped its original serial approach and rolled out a hybrid parallel/serial technology. Called SerialSwitch, it runs at 1.6 Gbytes/s in parallel mode and up to 6.4 Gbytes/s in serial mode per channel.
SPMT group members include ARM, Hynix, LG, Marvell, Samsung and Silicon Image. The first SPMT-based DRAMs are due by year’s end.
Rambus’ Mobile XDR, meanwhile, reportedly delivers up to 17 Gbytes/s of bandwidth. But Rambus burned bridges in an earlier attempt to push its technology for PC main memory, and any ill will that lingers from that affair might work against its new spec.
Mobile XDR addresses “the shortcomings” of LPDDR3, said Gebhart. LPDDR3 is “well over” the industry goal of meeting a power consumption threshold of 500 mW in the future, he said. “There is plenty of bandwidth [with LPDDR3], but the power is way too high.”
What’s next? Some market trackers are already talking about LPDDR4, which may or may not materialize. Another technology to watch is M-PHY, backed by the Mobile Industry Processor Interface Alliance. MIPI’s spec is for a chip-to-chip interface for display, camera, audio, video, memory, power management and communications from baseband to RF chip. It is indirectly competitive with mobile DRAM, but it has some implications for memory.
|Mobile DRAM pricing is driven by cost reductions rather than the fluctuations of supply and demand