Spec turns USB3 into chip link

SAN JOSE, Calif. – Two industry groups are pooling their technologies to define a new high speed, low power chip-to-chip interface for next generation mobile silicon. The USB 3.0 Promoters Group and the MIPI Alliance hope to finish and make available a joint specification early next year.

The so-called Superspeed Inter-Chip spec (SSIC) aims to support physical layer data rates starting at 1.2 to 2.9 Gbits/s and eventually extending up to 5.8 Gbits/s. It also plans a low power mode for data rates between 10 Kbits/s and 600 Mbits/s.

SSIC targets power consumption of about 1-5 picojoules per bit/second, depending on the mode used. In high-speed mode that may amount to an average of about 20 mW.

The effort essentially marries the M-PHY spec, a low power physical layer technology defined by the MIPI Alliance, with the media access controller and higher layer software of the USB 3.0 spec. A working group under the USB 3.0 Promoters Group including members of Intel, ST Ericsson and Texas Instruments started working on the details of the spec about a month ago.

The working group is now deciding what if any parts of the USB 3.0 spec to make optional because they may not be needed in a chip interface. "We wanted to lower the cost of design and time to market by leveraging existing IP—it's about software reuse," said Brian Carlson, vice chair of MIPI and Omap product manager at TI.

SSIC aims to be follow-on of Inter-Chip Connectivity (ICC), a chip interface based on the 480 Mbit/s USB 2.0 spec developed privately by chip designer SMSC (Hauppauge, NY). SMSC started licensing the technology in June and signed up Qualcomm and AMD earlier this year. It makes its spec available free to host chip designers and for a one-time $100,000 fee to peripheral chip designers.

SSIC would be royalty free to all adopter-level members of the MIPI Alliance and the USB 3.0 Promoters group who want to use it in chips for what Carlson described as "mobile terminals with voice capability," including Wi-Fi devices with VoIP features. Vendors could license the technology on a reasonable and non-discriminatory (RAND) basis for other kinds of chips or systems.

The need is clear. Multiple vendors of applications processors are already designing their own next-generation chip interfaces due to a lack of a standard for the kind of high throughput, low power link they need.

For its part, the MIPI Alliance hopes to establish its M-PHY as a general purpose chip-to-chip interface. It has already specified the technology as the basis for six of its own existing or pending interconnect standards. Jedec has also adopted M-PHY as part of its UFS flash memory interface.