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EDA vendor rolls hierarchical 3-D extractor
Dylan McGrath
5/18/2011 7:41 PM EDT
SAN FRANCISCO—EDA vendor Silicon Frontline Technology Inc. (SFT) announced Wednesday (May 18) what it claims is the industry's first commercial hierarchical 3-D extractor, H3D, for post-layout verification.
SFT (Campbell, Calif.) said H3D offers hierarchical parasitic extraction, hierarchical netlisting, unlimited capacity and field-solver accuracy. The tool works with design flows from leading EDA suppliers, according to SFT.
"Post-layout verification is a major bottleneck in today’s leading edge designs," said Yuri Feinberg, CEO of SFT, in a statement. "With the introduction of H3D, this bottleneck is removed by providing an accurate extractor that runs with sub-linear performance and delivers a hierarchical output which enables post-layout simulation speed up."
According to SFT, H3D is suited for array-based and repetitive design structures, including memories, FPGAs and image sensors. The tool's extraction performance is sub-linear, which ensures as design size grows extraction performance improves, according to the company.
SFT said H3D's hierarchical extraction results are design dependent, but claimed that the company has demonstrated shown performance improvements from 20-120x when compared to flat extraction.
The extraction tool is built on a hierarchical random walk algorithm, giving users the ability to specify the accuracy required on a net by net or block by block basis, SFT said. H3D provides unlimited capacity due to its hierarchical extraction and parallelization, the company said.
The hierarchical output supports R, C, distributed RC and RCCc, according to SFT.
H3D is shipping early in the third quarter. Pricing information was not provided.
SFT (Campbell, Calif.) said H3D offers hierarchical parasitic extraction, hierarchical netlisting, unlimited capacity and field-solver accuracy. The tool works with design flows from leading EDA suppliers, according to SFT.
"Post-layout verification is a major bottleneck in today’s leading edge designs," said Yuri Feinberg, CEO of SFT, in a statement. "With the introduction of H3D, this bottleneck is removed by providing an accurate extractor that runs with sub-linear performance and delivers a hierarchical output which enables post-layout simulation speed up."
According to SFT, H3D is suited for array-based and repetitive design structures, including memories, FPGAs and image sensors. The tool's extraction performance is sub-linear, which ensures as design size grows extraction performance improves, according to the company.
SFT said H3D's hierarchical extraction results are design dependent, but claimed that the company has demonstrated shown performance improvements from 20-120x when compared to flat extraction.
The extraction tool is built on a hierarchical random walk algorithm, giving users the ability to specify the accuracy required on a net by net or block by block basis, SFT said. H3D provides unlimited capacity due to its hierarchical extraction and parallelization, the company said.
The hierarchical output supports R, C, distributed RC and RCCc, according to SFT.
H3D is shipping early in the third quarter. Pricing information was not provided.
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