EDA earns mixed grades in latest report card

SAN DIEGO—The proverbial analyst of the EDA industry predicted that design automation tools will become a $6.6 billion industry by 2015.

But that watershed mark will only happen if EDA as an industry not only takes its responsibility for developing design tools that enable the IC design process seriously, but also "at a design cost that allows the ecosystem to operate at a profit," proclaimed Gary Smith.

"This is not about cost of EDA tools—that’s lunch money," remarked Smith at the Design Automation Conference here. "What I’m talking about is the level of automation; the costs are in the engineers to do the design."

The principal of Gary Smith EDA, Inc. said that "if we can keep the cost of designing a SoC below $25 million the VCs will start funding semiconductor start-ups again." He added that if that cost is above $50 million even IDMs will not be able to afford to do many designs.

Smith was adamant in stating that the EDA industry, as a whole, is responsible for developing a level of automation that allows the design process to be affordable. That cannot be done with today’s makeup of design teams.

Today's design team size ranges from 100 to 200 engineers, said Smith. The design team size "for 104 million gates should be 30 hardware design engineers for a cost of $18.7 million," said Smith. He offered a divide & conquer approach by bringing down the number of blocks a designer handles from the usual 25 to 35 today down to 5. "Anything over that slows down the design significantly and drives up the cost."

Smith said using a platform design methodology can reduce the number of engineers assigned per block among designers, integrators and verification engineers needed from 36 to 24 for a 100 million gate design. As far as tools are concerned Smith ideally an EDA tool should be able to handle 20 million gates in "average" high-end designs.

Smith's number one peeve: "We still have far too many R&D engineers that don’t have the slightest idea how design engineers use their tools." He called on all industry participants to get involved in the ‘software productivity’ problem, lest the EDA tools become irrelevant in chip designs. As far as the "big three" EDA companies are concerned, Smith rated currently as number 1,2,3 technology leaders as Synopsys, followed by Mentor Graphics and Cadence.

At a company event Monday here, Walden Rhines, chairman and CEO of Mentor Graphics had his own assessment of his company’s triumphs: "We had a record year and we anticipate another enjoyable $1 billion year." Rhines also lauded the three new directors which last month were added to the Mentor Graphics Board--Jose Maria Alapont, Gary Meyers and David Schechter, "who already have opened new doors and are instrumental in giving our shareholders more value."