unified memory and programming models
Rogers said that current heterogeneous multicore architectures are currently constrained by the programming model and communications overheads. "The good news is the Fusion System Architecture blows away both of these constraints," he said. "Where we're headed is the architected era. We make the GPU into a peer processor rather than a device," he said
Rogers outlined a roadmap that includes support for C++ features, unification of the address space, support for nested data parallelism, user-mode scheduling for lower latency task dispatch between CPUs and GPUs, and the addition of pre-emption and context switching.
Automated lower balancing between CPU and GPU is part of that progress, according to Rogers. In addition, specific FSA enhancements will be supported by newer programming languages and interfaces such as OpenCL and DirectCompute. One of the next steps will be the addition of bi-directional power management to CPU, GPU combinations. But the key is the creation of a unified memory address space and fully coherent memory shared by the CPU and GPU so they operate seamlessly together, Rogers said.
What was not made clear in what was essentially a technical presentation is how AMD, as one of a number of implementors and contributors to the Fusion System Architecture will make its money from the development of Fusion.
Related links and articles:
Keynote could be found at http://developer.amd.com/afds/pages/rebroadcast2.aspx
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