Killing bugs in PCIe Gen 3 products
Work has so far focused on electric and analog aspects of the physical-layer design for PCIe Gen 4. Over time, exploration will start on logical-layer and protocol improvements in areas such as latency reduction, forward error correction, deeper pipelining and error reporting and control.
At the end of the day, costs are expected to increase with the new generation, especially for applications that need to maintain today's longer distances. But the group aims to keep additional costs to a minimum.
"PCI Express lives and breathes because of its ubiquity and that comes based on its low cost," said Neshanti.
The need for speed is clear. Graphics and network switches are among the most bandwidth-hungry applications driving Gen 4. Designers of dual-port 40 Gbit/s Ethernet and single-port 100G Ethernet boards want Gen 4 to avoid the costs of supporting the pins they otherwise need for 16 lanes of PCIe Gen 3.
"Adapter vendors like to be around [eight-lane] implementations for cost reasons," said Yanes.
Meanwhile, engineers are making progress getting 8 GT/s PCIe 3.0 products out the door. At least 14 companies with building block cores, software or testers have announced Gen 3 support.
To date about 23 adapter cards and 19 systems from top PC makers have participated in the PCI SIG's Gen 3 plugfests. "Their products are in prototype phase and haven’t achieved full debug interoperability, so they are not ready to announce them," said Yanes.
The PCI SIG hopes to publish by early next year a list of products that have passed interop tests. The group plans at least three more plugfests in Silicon Valley and Taiwan this year.
"PCI Express Gen 3 is more sophisticated in its electrical design [than past PCI SIG standards], so we are giving members more feedback on how they are doing" with their first products, said Neshanti.
Anticipating the future, PLX Technology demoed at the PCI dev con eight lanes of PCI Express 3.0 linking systems over optical cables at 64 Gbits/s.