IBM reports drift-tolerant multilevel cell PCM

6/30/2011 7:07 PM EDT

Yes

7/1/2011 4:49 AM EDT

Ron Neale has written a series of articles published on the EE Times Memory Design Line pages that review the published literature and make extrapolations that highlight the issue of current density.

There is also the issue of the thermal cross-talk as writes take place in cells that are closely packed.

As to why 1-Gbit, sub-90-nm devices from Micron and Samsung are difficult to see in the wild, perhaps they are shy creatures that rarely come down to watering holes.

7/1/2011 9:29 AM EDT

PCM needs p-n junction to provide current, but adjacent junctions form parasitic p-n-p.

7/1/2011 4:53 AM EDT

I didn't focus on the speed claims because the 'stair-case up' writing algorithm actually makes multi-level cell PCM slower than single-bit PCM.

You have write four or five times to the cell using the iterative algorithm to store 2 bits.

7/1/2011 12:28 PM EDT

Does that mean that the write operation is nondeterministic? Does the write operation depend on the current state of the cell because you step through the states? Or does it zero the cell and then step it up to the desired value?

Larry M.

7/1/2011 9:09 AM EDT

That reminds, if the chip size doubles just to handle the new 2-bit coding, we didn't gain anything.

7/1/2011 12:45 PM EDT

Mr. Pozidis and his whole team are no scientists but a bunch of fraudsters (until recently touting another scam, the "nanomechanical" storage). Since Ovonyx' and Intel's unfortunate experiments with multi-bit PCM, it has been well known that the drift increases exponentially with temperature. So in a hot day or in a busy server room, the "new" IBM memory will last a day, even if it had the best error correction in the world. Not to mention that their chip apparently cannot store more than 50K bytes even without error correction (a lowly 8Gbyte NAND chip stores 170,000x more data).

IBM knows very well that PCM is a scam and the longest-running techno Ponzi. PCM simply cannot scale, is too expensive, has horrible density, and is extremely slow and power-hungry in write. IBM, like every other PCM advocate in the past, has a good reason to engage in the techno-Ponzi - they are losing market share in the enterprise storage space and are desperate. Just like Micron was in the 1990s when the Asian attacked, just like Intel was 10 years ago as NOR lost to NAND, just like Samsung was when it failed to gain share in the NOR business.

PCM will never be commercialized in volume. No product on the market uses any PCM - neither Micron nor Samsung have any sales. IBM is insulting the intelligence of its potential customers.

7/4/2011 6:02 AM EDT

Grüzi, Volatile Memory. The model cellphone using PCM is the Samsung GT-E2550 GSM. It was actually reported on in EE Times last month. Here is the article http://www.eetimes.com/electronics-news/4215679/Chipworks-tears-down-Samsung-PCM-phone

7/4/2011 1:34 PM EDT

IBMZRL: Are you one of the millipede fraudsters at IBM? Samsung GT-E2550 GSM is NOT A SMART PHONE! It is a basic, old 2G phone. MOREOVER, I DO OWN a Samsung GT-E2550 handset and it has absolutely no PCM in it - it has plain old NOR. The Chipworks busybees destroyed a non-commercial, planted phone. Samsung removed all the PCM from the production GT-E2550 series after encountering power consumption issues a year ago.

7/4/2011 2:06 PM EDT

I love your passion Volatile Memory. I see you can be traced to a similar argument back in December 2010. Regardless, let me know your email address and in 2016 we can catch up.

7/4/2011 1:37 PM EDT

yalanand: Even the two levels are unstable, as Mr. Neale has shown. Why do you think Intel/STM/Numonyx/Micron never produced stable MLC PCM?

7/4/2011 7:24 PM EDT

It is not limited to four levels (2-bits).

As Haris Pozadis of IBM was quoted saying in the article: "We don't believe there is a fundamental limitation. We believe we can extend this to 3-bits, even 4-bits per cell."

7/4/2011 9:17 PM EDT

You can demonstrate multiple resistance levels, but the more levels you have, the less difference between levels, in terms of amount of amorphous material. As you scale down, this decreasing difference becomes more difficult to control. So you might see 90 nm MLC demo, but 45 nm is more difficult.

This applies to scaling down any multibit cell - you're actually scaling the intracell bit size even faster (2x, 3x, etc.). So it's much more risky.

7/7/2011 8:54 AM EDT

Scaling to 3x, 4x is extremely unlikely...there is simply no voltage headroom to do that...Kris

7/7/2011 4:00 PM EDT

NAND was about to hit the scaling wall in 2003, according to the all-knowing perpetrators of the techno-Ponzi (for example, read public statements by Stefan Lai at Intel). The fact is, NAND scales quite well and will continue to scale quite well. Therefore, the next gen memory is NAND.

Techno-Ponzi is a term which I believe was coined by Mr. David Manners. Loosely, it describes a bunch of scamsters that take money from management and investors by promising to develop technical devices or products that are always just over the horizon. PCM is the longest-running techno-Ponzi, since its "invention" in late 1960s.

Read this:

http://www.electronicsweekly.com/blogs/david-manners-semiconductor-blog/2011/01/techno-ponzi-memory-re-emerges.html

and this:

http://www.electronicsweekly.com/blogs/david-manners-semiconductor-blog/2009/08/ten-best-techno-ponzi-schemes.html

7/8/2011 1:00 AM EDT

NAND has been starting to have scaling difficulties recently, but continues to be extended, mainly with system-level improvements. So in the end we may have to judge the technology not only at the device level but also at the system level.