drift-tolerance via encoding
However, because of structural relaxation of the atoms in the amorphous state, the resistance increases over time after the phase change, eventually causing errors in the read-out, IBM said. To overcome this IBM applied a coding technique that they claim is tolerant to drift. The technique is based on the fact that, on average, the relative order of programmed cells with different resistance levels does not change due to drift. Therefore by encoding data in a code word that is applied to cluster of memory cells, in this case 7, it is possible to improve the bit error rate at the expense of bit density
IBM reported 1.57 bits per cell with a 1 in 100,000 bit error rate after 37 days at room temperature. This is before the use of conventional error-correction codes that could bring the overall error rate down to levels around 1 in 10^15 or less, which are required for practical memory devices, the authors said in the paper.
Pozadis said: "We don't believe there is a fundamental limitation. We believe we can extend this to 3-bits, even 4-bits per cell." He confirmed that the use of iterative programming and coding has implications for slower program and read times. There is also a die area penalty, he said because of the use of reference cells and the need to provide encode/decode hardware.
The PCM test chip was designed and fabricated by scientists and engineers located in Burlington, Vermont; Yorktown Heights, New York and in Zurich.
The paper Drift-tolerant Multilevel Phase-Change Memory by N. Papandreou, H. Pozidis, T. Mittelholzer, G.F. Close, M. Breitwisch, C. Lam and E. Eleftheriou, was presented by Pozidis at the IEEE International Memory Workshop held in May 2011 in Monterey, California.
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