MANHASSET, NY -- A research firm has determined that fully depleted silicon-on-insulator wafers are more cost effective compared to bulk silicon for processing semiconductor devices at the 22nm technology node.
Research firm IC Knowledge LLC, specializing in semiconductor cost analysis, has completed a comprehensive cost analysis that determined FD-SOI’s fewer total processing steps offers a simpler overall process flow.
FD-SOI processing dramatically decreases the number of implant masks and implant steps needed which “enables FD-SOI’s greater cost efficiency,” according to Scotten W. Jones, president of IC Knowledge, adding that “fully depleted SOI is the key,”
IC Knowledge worked with a wafer-processing consultant and Soitec, SOI wafer manufacturer, to define three sample process flows representative of state-of-the-art industry practices for the 22 nm node: one planar bulk CMOS and two versions of FD-SOI – with implanted source/drain or with in-situ doped source/drain.
All process flows assumed three threshold voltages, dual gate oxides and suitability for system-on-a-chip (SOC) applications.
The bulk CMOS process assumed a suite of mobility-enhancing stressors. The two FD-SOI process flows, on top of relevant mobility-enhancing stressors, also assumed multiple features such as n+ and p+ back-gates and n-well and p-well implants under the buried oxide (BOx) layer, access to the n-well and p-well, two shallow-trench isolation depths and electro-static discharge devices in a bulk area.
The same gate integration schemes (gate-last high-k metal gate) and number of metal layers (eight) were assumed in all scenarios. For SOI, a volume pricing of $500 per starting wafer was added. For bulk silicon, an aggressive price of $130 per (epi) starting wafer was selected.
IC Knowledge then evaluated how each process flow would perform in a Taiwanese wafer fab producing 30,000 wafers per month in the 2012 timeframe.
The cost model scenario generator considered the costs of starting wafers, direct and in-direct labor, depreciation of the wafer fab, equipment maintenance, monitor wafers, facilities such as electricity, and consumables such as reticle sets, gases and chemicals. Calculations of the cost per wafer yielded used in the model have been validated by IC Knowledge using wafer cost data collected from fabs throughout the semiconductor industry.
The analysis determined that the most economical yielded-wafer cost was achieved by FD-SOI processing with in-situ doped source/drain, at approximately $3,000 per wafer. Furthermore, both versions of FD-SOI were determined to be extremely cost competitive compared to bulk CMOS.
The study found only about one percent difference in the cost of yielded processed wafers produced by the second FD-SOI option – with implanted source/drain – and bulk CMOS.
The findings do not address FD-SOI’s superiority to bulk silicon in producing semiconductors with lower leakage and faster processing speeds or compare the performance of SOI and bulk silicon in processing multi-gate transistors at the 22 nm node and beyond. The analysis
is purely based on cost.