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Synopsys appoints director, tackles 20nm designs
Nicolas Mokhoff
7/15/2011 10:34 AM EDT
MANHASSET, NY -- Synopsys has appointed the current President of the University of Southern California (USC) Chrysostomos L. "Max" Nikias to its Board of Directors, effective July 11. 2011.
"Max brings to our board an extensive background in electrical engineering and insight into developing global technology trends," said Aart de Geus, chairman and CEO of Synopsys, Inc., in a statement. "As an internationally recognized engineer and the leader of one of the world's great institutions of higher learning, Max will be valuable in helping us shape our corporate strategy for the benefit of our customers, investors, partners and employees."
Nikias holds a bachelor's degree in electrical and mechanical engineering from the National Technical University of Athens, and an M.S. and Ph.D. in electrical engineering from the State University of New York at Buffalo. He is a member of the National Academy of Engineering and fellow of the IEEE and the American Association for the Advancement of Science (AAAS).
During his 20-year career at USC Nikias has been credited with recruiting new academic leadership, strengthening the academic medical enterprise, solidifying engineering as a top-tier school, attracting a series of major donations, creating innovative cross-disciplinary programs, enhancing globalization efforts and increasing support for students.
With the addition of Dr. Nikias, seven of Synopsys' nine Board of Directors members are independent.
20nm work
Synopsys has recently achieved a critical milestone with the successful tapeout of the first 20-nm test chip based on Samsung's High-k metal gate (HKMG) process technology.
The 20-nm tapeout represents the outcome of early R&D collaboration between Samsung and Synopsys aimed at developing and validating a comprehensive design implementation infrastructure for the next generation of 20-nm gigascale ICs. Key 20-nm design enablement innovations developed as part of the collaboration include modeling of new device structures, double-patterning-aware place-and-route and In-Design physical verification technology, and coding of advanced routing and design rule checking.
"Synopsys' technology leadership enabled us to quickly implement and validate our first 20-nanometer test chip. The successful tapeout of this test chip marks a critical milestone towards design readiness for our 20-nm process technology." said Kyu-Myung Choi, vice president of System LSI infrastructure design center, Device Solutions, Samsung Electronics, in a statement.
Separately the company recently announced IC Compiler-Advanced Geometry, a new configuration of its IC Compiler physical design product. IC Compiler-Advanced Geometry targets design support for double-patterning technology, which has emerged as a key requirement for the next generation of silicon technology at 20 nanometers (nm) and imposes strict constraints on placement, routing and physical verification.
Double-pattern technology requires a place-and-route tool to accurately generate a layout where each candidate layer can be decomposed into dual alternating patterns without undue impact on performance and device area.
The new configuration of IC Compiler includes technology to formulate double patterning (DPT) requirements as a generalized coloring problem, avoiding any potential conflicts and rendering a correct-by-construction solution that can be reliably decomposed during manufacturing.
"IC Compiler-Advanced Geometry is the industry's first DPT-compliant place-and-route solution that will provide designers moving to 20nm with an advanced solution that effectively meets the new challenges," said Antun Domic, senior vice president and general manager of Synopsys' Implementation Group.
"Max brings to our board an extensive background in electrical engineering and insight into developing global technology trends," said Aart de Geus, chairman and CEO of Synopsys, Inc., in a statement. "As an internationally recognized engineer and the leader of one of the world's great institutions of higher learning, Max will be valuable in helping us shape our corporate strategy for the benefit of our customers, investors, partners and employees."
Nikias holds a bachelor's degree in electrical and mechanical engineering from the National Technical University of Athens, and an M.S. and Ph.D. in electrical engineering from the State University of New York at Buffalo. He is a member of the National Academy of Engineering and fellow of the IEEE and the American Association for the Advancement of Science (AAAS).
During his 20-year career at USC Nikias has been credited with recruiting new academic leadership, strengthening the academic medical enterprise, solidifying engineering as a top-tier school, attracting a series of major donations, creating innovative cross-disciplinary programs, enhancing globalization efforts and increasing support for students.
With the addition of Dr. Nikias, seven of Synopsys' nine Board of Directors members are independent.
20nm work
Synopsys has recently achieved a critical milestone with the successful tapeout of the first 20-nm test chip based on Samsung's High-k metal gate (HKMG) process technology.
The 20-nm tapeout represents the outcome of early R&D collaboration between Samsung and Synopsys aimed at developing and validating a comprehensive design implementation infrastructure for the next generation of 20-nm gigascale ICs. Key 20-nm design enablement innovations developed as part of the collaboration include modeling of new device structures, double-patterning-aware place-and-route and In-Design physical verification technology, and coding of advanced routing and design rule checking.
"Synopsys' technology leadership enabled us to quickly implement and validate our first 20-nanometer test chip. The successful tapeout of this test chip marks a critical milestone towards design readiness for our 20-nm process technology." said Kyu-Myung Choi, vice president of System LSI infrastructure design center, Device Solutions, Samsung Electronics, in a statement.
Separately the company recently announced IC Compiler-Advanced Geometry, a new configuration of its IC Compiler physical design product. IC Compiler-Advanced Geometry targets design support for double-patterning technology, which has emerged as a key requirement for the next generation of silicon technology at 20 nanometers (nm) and imposes strict constraints on placement, routing and physical verification.
Double-pattern technology requires a place-and-route tool to accurately generate a layout where each candidate layer can be decomposed into dual alternating patterns without undue impact on performance and device area.
The new configuration of IC Compiler includes technology to formulate double patterning (DPT) requirements as a generalized coloring problem, avoiding any potential conflicts and rendering a correct-by-construction solution that can be reliably decomposed during manufacturing.
"IC Compiler-Advanced Geometry is the industry's first DPT-compliant place-and-route solution that will provide designers moving to 20nm with an advanced solution that effectively meets the new challenges," said Antun Domic, senior vice president and general manager of Synopsys' Implementation Group.
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