News & Analysis
Viewpoint: Will tri-gate play key role in Intel-ARM tussle?
Deepak Sekar
8/9/2011 12:25 AM EDT
Editor's note: The author of this viewpoint is the chief scientist at MonolithIC 3D Inc., an IP that markets technology for fabricating three-dimensional ICs which differs from Intel's tri-gate technology.
Rivalries between companies have a charm of their own. For many years, Intel v. AMD was the talk of the town, and then it became Microsoft v. Google. The most interesting rivalry today is, of course, Intel v. ARM. After Intel's tri-gate transistor announcement, I was therefore not surprised to see these news articles:
eWeek
3-D transistor will indeed help Intel beat back ARM, iHS iSuppli says
xbit Labs
ARM Not Afraid of Intel's 22nm/Tri-Gate Process Technology - Company.
Wired Revolution
Intel’s 3D tri-gate Transistor Redesign Brings Huge Efficiency Gains
At the moment, it certainly looks as though ARM will go planar at the 22-nm node, while Intel will go tri-gate. To judge if tri-gate offers Intel a significant advantage, a few questions need to be answered:
• Intel announced that their 22-nm tri-gate transistor consumed 50 percent lower power when compared to their 32-nm planar transistor. But what are the power savings for a 22-nm tri-gate transistor when compared to a 22-nm planar transistor?
• How much chip power can one save by using a 22-nm tri-gate transistor in a microprocessor instead of a 22-nm planar transistor? Is it 10 percent? Or is it 30 percent? Or is it 50 percent?
It is not difficult to get estimates for these. Let’s take a look.
Transistor-level calculations
Intel showed some detailed transistor I-V curves in their press briefing. These are reproduced in Fig. 1. Using this data, you get the information shown in Fig. 2. You’ll notice that the 22-nm tri-gate transistor can give a 140mV supply voltage reduction compared to the 22-nm planar transistor. The 22-nm tri-gate transistor also provides a 50 percent power reduction compared to the 32-nm planar transistor, but this advantage drops to 19 percent when compared to the 22-nm planar transistor.
Figure 2: Transistor-level comparisons of tri-gate and planar transistors.
Chip-level calculations
I then used IntSim, an open-source IC simulator, to estimate benefits of tri-gate transistors at the chip level. IntSim has models that describe various aspects of a modern-day chip, and its results show a good fit to actual data from past Intel microprocessors. For more details, please refer to Fig. 3 and the original paper about IntSim at the 2007 International Conference on Computer-Aided Design (ICCAD). A GUI-based version of IntSim is available at this link (for free use).
For this study, I considered a 1-GHz mobile logic core built with either (1) 22-nm planar transistors, or (2) 22-nm tri-gate transistors. Since Intel presented only relative numbers for transistor performance, I took numbers from the International Technology Roadmap for Semiconductors (ITRS) and scaled them based on Fig. 2.
Results from IntSim are shown in Fig. 4.
• The 140mV supply voltage reduction enabled by the tri-gate device is useful, since it saves both clock and wire power. Fig. 4 indicates a 28 percent reduction in clock power and wire power.
• Transistor drive resistance, which is proportional to the ratio of supply voltage to drive current, is reduced with the tri-gate transistor. Hence, it is easier to drive wire capacitance and gates can be made smaller for the same performance target. This, coupled with the transistor power benefits shown in Fig. 2, gives a 28 percent power reduction for logic gates in the design.
• Repeater power goes down by 32 percent due to the better-quality transistors.
Overall, ~28 percent power reduction can be obtained by using a tri-gate transistor instead of a planar transistor for a 22-nm microprocessor core. This is quite significant. Kudos to Intel’s technology team!
Implications to the Intel-ARM tussle
As an engineer, I really like the fact that Intel is taking the tri-gate transistor into manufacturing—it is a fantastic technical achievement.
But will it play an important role in the Intel-ARM tussle? I don't think so. Let me explain why.
There are several variables involved in the Intel-ARM equation:
• ARM has momentum in the mobile space. I've learned, in my past, that displacing a technology or product entrenched in the marketplace is very difficult.
• Intel's x86 architecture is CISC. Advanced RISC machines, better known as ARM, use a RISC architecture. RISC architectures have historically given higher performance per watt than CISC in the mobile space. Can x86 bridge this gap?
• Intel chips are one process generation ahead of ARM chips. This is a valuable advantage.
• ARM chips are typically made in low-cost fabs in the Far East. For example, fabs in Taiwan are known to be 20-50 percent cheaper than fabs in the U.S., at the same technology node. This is due to additional government incentives, tax breaks, lower building costs and lower labor costs. All these years, having fabs in the U.S. did not impact Intel, since its only competition was AMD, which itself had not-so-cheap fabs in Europe. But while competing with ARM, low-cost fabs could be important.
• There are far more suppliers of ARM chips than x86 ones. Customers like competition as it keeps prices down.
• Who will be the first to "productize" other breakthrough technologies, such as 3-D stacking of DRAM atop logic, and monolithic 3-D? Intel or ARM? Some of these technologies could provide more benefits to mobile chip power, performance and die size than tri-gate.
• Intel has a lot more resources than players in the ARM world - this could be useful, especially in this day and age when designs cost $100M, fabs cost $5B and process R&D costs $1B.
• Will Microsoft execute on its goal to get Windows 8 on ARM? How soon and how well will it execute? This is a crucial business issue for laptops and netbooks, but may not impact the smart-phone world much.
Bottom line: The tri-gate transistor is a major engineering achievement, but I doubt if it will play a key role in the Intel-ARM tussle. In my opinion, many of the points mentioned above are more important.
Dr. Deepak Sekar is the chief scientist of MonolithIC 3D Inc. Author or co-author of a book, an invited book chapter, 15 publications and 55 issued or pending patents, he serves as a program committee co-chair at the International Interconnect Technology Conference.
Rivalries between companies have a charm of their own. For many years, Intel v. AMD was the talk of the town, and then it became Microsoft v. Google. The most interesting rivalry today is, of course, Intel v. ARM. After Intel's tri-gate transistor announcement, I was therefore not surprised to see these news articles:
eWeek
3-D transistor will indeed help Intel beat back ARM, iHS iSuppli says
xbit Labs
ARM Not Afraid of Intel's 22nm/Tri-Gate Process Technology - Company.
Wired Revolution
Intel’s 3D tri-gate Transistor Redesign Brings Huge Efficiency Gains
At the moment, it certainly looks as though ARM will go planar at the 22-nm node, while Intel will go tri-gate. To judge if tri-gate offers Intel a significant advantage, a few questions need to be answered:
• Intel announced that their 22-nm tri-gate transistor consumed 50 percent lower power when compared to their 32-nm planar transistor. But what are the power savings for a 22-nm tri-gate transistor when compared to a 22-nm planar transistor?
• How much chip power can one save by using a 22-nm tri-gate transistor in a microprocessor instead of a 22-nm planar transistor? Is it 10 percent? Or is it 30 percent? Or is it 50 percent?
It is not difficult to get estimates for these. Let’s take a look.
Transistor-level calculations
Figure 1: Transistor I-V characteristics shown in Intel’s press announcement.
Intel showed some detailed transistor I-V curves in their press briefing. These are reproduced in Fig. 1. Using this data, you get the information shown in Fig. 2. You’ll notice that the 22-nm tri-gate transistor can give a 140mV supply voltage reduction compared to the 22-nm planar transistor. The 22-nm tri-gate transistor also provides a 50 percent power reduction compared to the 32-nm planar transistor, but this advantage drops to 19 percent when compared to the 22-nm planar transistor.
Figure 2: Transistor-level comparisons of tri-gate and planar transistors.
Chip-level calculations
I then used IntSim, an open-source IC simulator, to estimate benefits of tri-gate transistors at the chip level. IntSim has models that describe various aspects of a modern-day chip, and its results show a good fit to actual data from past Intel microprocessors. For more details, please refer to Fig. 3 and the original paper about IntSim at the 2007 International Conference on Computer-Aided Design (ICCAD). A GUI-based version of IntSim is available at this link (for free use).
Figure 3: IntSim, a chip simulator, was used for this analysis.
For this study, I considered a 1-GHz mobile logic core built with either (1) 22-nm planar transistors, or (2) 22-nm tri-gate transistors. Since Intel presented only relative numbers for transistor performance, I took numbers from the International Technology Roadmap for Semiconductors (ITRS) and scaled them based on Fig. 2.
Figure 4: Power savings estimated with IntSim.
Results from IntSim are shown in Fig. 4.
• The 140mV supply voltage reduction enabled by the tri-gate device is useful, since it saves both clock and wire power. Fig. 4 indicates a 28 percent reduction in clock power and wire power.
• Transistor drive resistance, which is proportional to the ratio of supply voltage to drive current, is reduced with the tri-gate transistor. Hence, it is easier to drive wire capacitance and gates can be made smaller for the same performance target. This, coupled with the transistor power benefits shown in Fig. 2, gives a 28 percent power reduction for logic gates in the design.
• Repeater power goes down by 32 percent due to the better-quality transistors.
Overall, ~28 percent power reduction can be obtained by using a tri-gate transistor instead of a planar transistor for a 22-nm microprocessor core. This is quite significant. Kudos to Intel’s technology team!
Implications to the Intel-ARM tussle
As an engineer, I really like the fact that Intel is taking the tri-gate transistor into manufacturing—it is a fantastic technical achievement.
But will it play an important role in the Intel-ARM tussle? I don't think so. Let me explain why.
There are several variables involved in the Intel-ARM equation:
• ARM has momentum in the mobile space. I've learned, in my past, that displacing a technology or product entrenched in the marketplace is very difficult.
• Intel's x86 architecture is CISC. Advanced RISC machines, better known as ARM, use a RISC architecture. RISC architectures have historically given higher performance per watt than CISC in the mobile space. Can x86 bridge this gap?
• Intel chips are one process generation ahead of ARM chips. This is a valuable advantage.
• ARM chips are typically made in low-cost fabs in the Far East. For example, fabs in Taiwan are known to be 20-50 percent cheaper than fabs in the U.S., at the same technology node. This is due to additional government incentives, tax breaks, lower building costs and lower labor costs. All these years, having fabs in the U.S. did not impact Intel, since its only competition was AMD, which itself had not-so-cheap fabs in Europe. But while competing with ARM, low-cost fabs could be important.
• There are far more suppliers of ARM chips than x86 ones. Customers like competition as it keeps prices down.
• Who will be the first to "productize" other breakthrough technologies, such as 3-D stacking of DRAM atop logic, and monolithic 3-D? Intel or ARM? Some of these technologies could provide more benefits to mobile chip power, performance and die size than tri-gate.
• Intel has a lot more resources than players in the ARM world - this could be useful, especially in this day and age when designs cost $100M, fabs cost $5B and process R&D costs $1B.
• Will Microsoft execute on its goal to get Windows 8 on ARM? How soon and how well will it execute? This is a crucial business issue for laptops and netbooks, but may not impact the smart-phone world much.
Bottom line: The tri-gate transistor is a major engineering achievement, but I doubt if it will play a key role in the Intel-ARM tussle. In my opinion, many of the points mentioned above are more important.
Dr. Deepak Sekar is the chief scientist of MonolithIC 3D Inc. Author or co-author of a book, an invited book chapter, 15 publications and 55 issued or pending patents, he serves as a program committee co-chair at the International Interconnect Technology Conference.
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sforce
8/9/2011 2:20 AM EDT
Fab cost is indeed a huge factor in this battle between Intel and ARM. I agree that ARM currently has the cost advantage, as most of the ARM chip manufacturing is done in Asia. However, it is no secret that Intel is building a fab in China, and with its huge war chest, it may start building fabs in other low cost Asian countries as well. As such, the battle is far from over, in fact it's just beginning.
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Deepak Sekar
8/9/2011 2:31 AM EDT
If you look at Intel's 22nm presentation, they talk about using 5 fabs for the technology, of which 4 are in the US and 1 is in Israel. The China fab is supposed to be two generations behind the leading edge... In the long term, Intel will either need to find a way to get additional US government concessions or move manufacturing offshore. Paul Otellini, the CEO of Intel, had some interesting comments about this issue here: http://www.eetimes.com/electronics-news/4209358/Intel-calls-for-manufacturing-tax-breaks
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resistion
8/9/2011 3:09 AM EDT
That's an interesting point. If Intel's Dalian fab stays at 65 nm, it will continue to lag behind the technology of its key products. It won't make sense until Intel China gets high-k, Wassenaar be damned.
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iniewski
8/9/2011 10:42 AM EDT
Very intriguing analysis Deepak!, I wonder how close you are to a real microprocessor designs...I agree with prediction that Intel fabs are going offshore unless various levels of governments provide substantial levels of incentives...the capital expenditures are just too high, Kris
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Deepak Sekar
8/9/2011 10:53 AM EDT
@ Kris and Resistion: Thanks for your comments.
For comparison of IntSim's results with commercial microprocessors, pls. see page 5 of the ICCAD 2007 paper (link provided in write-up above)
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Ron Wilson, Embedded.com
8/9/2011 11:50 AM EDT
I wonder if there are some important factors missing from system-level comparisons of Intel finFETs vs. planar MOSFETs. First, advanced planar design employs several different threshold voltages--an option not practical today with finFETs. Dynamic and leakage power comparisons would apply only to the small minority of lowest-slack nets.
Second, today's low-power designs use extensive clock throttling, clock-gating and power-gating, minimizing differences in both dynamic power and leakage. If the use profile is friendly, both chips would spend most of their time with their critical blocks gated off.
Third, finFET users give up much of their flexibility in transistor sizing. Only Intel seems to think this will not be a limitation in circuit design.
So while lowering the power rail a bit undoubtedly will reduce instantaneous dynamic power, this could turn out to be a second-order consideration at the chip level, and invisible at the system level, when display backlights, radios, and ill-conceived software get layered on top of the silicon.
ron
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pinhead
8/9/2011 12:27 PM EDT
Nice post, Ron. I love the line about ill-conceived software, too!
My armchair quarterbacking is that Intel doesn't think the finfet design rules are a problem because they're so digital focused. I'd guess that analog heavy designs will suffer a lot more under the restrictive ground rules and device options that finfets impose.
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Deepak Sekar
8/9/2011 12:37 PM EDT
Hi Ron, these are excellent questions.
Intel's trigate uses multiple Vt values, from what I hear... you can tune the Vt by changing the work function of the metal gate, etc.
IntSim considers the same amount of clock gating and power gating used for the tri-gate as compared to planar.
The loss of flexibility in transistor sizing would matter to a foundry quite a bit, I agree. An IDM would find it easier to adjust... especially if the amount of analog content is low.
I agree, also, with your comment that at the system level the benefits of trigate would be much smaller than at the transistor level or chip level... yup, things like ill-conceived software, as you quote above, can cause serious damage!! :-)
Does this answer your questions?
PS: Many manufacturers use similar methodologies as IntSim for pre-silicon design estimation. (eg) See this Intel paper (http://tinyurl.com/3ghgj24)
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pinhead
8/9/2011 1:21 PM EDT
By the way, thanks for the article Deepak. It was the most thought provoking piece on EETimes this AM - and judging from the amount of comments it's garnering, I'm not the only one that thinks so.
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iniewski
8/9/2011 1:10 PM EDT
Not sure why ill-conceived software is an issue here...are you saying there is a difference in writing the software for planar vs tri-gate technology??? Kris
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Deepak Sekar
8/9/2011 1:39 PM EDT
@Kris: Your comment is a good one, there is indeed no difference in writing the software between planar and tri-gate. I think Ron is saying software and other factors may impact system power consumption more than a better transistor.
@Pinhead: Thanks for your note above.
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Or_Bach
8/9/2011 2:11 PM EDT
Deepak's write-up is very well done, and raises a very important point for Intel. The current market dynamic in mobile is a classic disruptive trend, and will challenge Intel's dominance in laptops and desktops in the long term. Intel should clearly understand and attend to this situation. It has one of the best R&D teams and a very strong balance sheet.
But just doing what they been doing for the last 5 years falls into Einstein's famous statement about doing the same and expecting different results. Intel needs a leap-frog and not an incremental advantage. From my end, the answer is clear. If Intel becomes the first to bring out the monolithic 3D IC, it could bring powerfully competitive advantages to the company and tackle this strategic inflection point.
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Erik C.
8/9/2011 6:00 PM EDT
A very well-written article translating the fabrication advancement to system level gain. From the benchmarking method, it is based on the same on/off current ratio to compare the FinFET and planar device. However, it would also be interesting to compare the power saving by fixing the supply voltage but lowering the leakage current of the FinFET by 10x so that both high/low threshold voltages are covered (now it only covers the “low” case, which is the upper blue curve to the right of figure 1). On the logic gate level, it seems that more power could be saved because first, leakage power consumption is more than dynamic power consumption and second, linear voltage change results in exponential change of carrier-distribution and hence current. Although there could be a trade-off for “clock and wiring” power by using higher supply voltage, it would still be interesting to see the overall effect by considering both high/low threshold voltage choices. Probably there will even be some optimized choices for threshold voltage in a system level point of view. After all, the threshold voltage can always be tuned to satisfy different system application. But again, a very nice and quantitative article.
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Deepak Sekar
8/9/2011 6:11 PM EDT
@Erik:
I tried to see how much power one can save by keeping Vdd constant and getting lower leakage. The chip power savings were not as high as when Vdd is reduced. When Vdd is lowered, the clock and wire power also reduce, as you point out above. Since clock power + wire power can form more than 50% of total power, this is particularly useful.
Leakage is typically not more than 30% of the chip power in today's chips... If you see T. Sakurai's paper at ASP-DAC 2000, he explains why. Essentially, when you optimize Vdd and Vt for minimum power, the equations are such that leakage is not more than 30% of total power.
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iniewski
8/9/2011 6:39 PM EDT
One additional consideration that would be of interests: process variability. Does anyone has any opinion which of the two technologies offer more tightly controlled VT, Ion etc distributions?...Kris
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Deepak Sekar
8/9/2011 7:02 PM EDT
@Kris: Good question once again. Some studies I've seen say that the Finfet is better for Vt variability compared to the planar device (at the same Vdd), especially for SRAM. Lower susceptibility to random dopant fluctuations and better short channel characteristics seem to help!
This is valuable particularly for SRAM, and allows one to reduce the Vdd. Here is an easy-to-read EETimes article where IMEC's comparison of variability for planar transistors and Finfets are given:
http://www.eetimes.com/electronics-news/4217017/IMEC-benchmarks-FinFET
I'd like to see the official variability numbers from Intel when they publish them though... with variability, you never know for sure until you see rigorously collected data from manufacturing.
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Erik C.
8/9/2011 8:03 PM EDT
For a fully-depleted tri-gate, the fin can actually be left un-doped so there might be little Vt variation because of RDF. But the Vt would depend on many other factors such as dimension of the Fin, the line-edge-roughness (LER) of the surface, including both top and two sides. Other process variation could be from the raised S/D, which probably is done by selective epitaxial growth and depends not only on the Fin structure but also on the pattern density of the Fin. (I would imagine the design rule must be pretty different for the planar transistor.) Overall the process variation control for tri-gate must be much more difficult than planar transistor, but apparently it can still be done..
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abraxalito
8/9/2011 8:25 PM EDT
Engineers will always love technology, but customers love solutions. Not enough talk here about how ARM and Intel are addressing customers' requirements. VHS saw off Betamax despite being technologically inferior. Trigate or not, technology is mainly a red herring in terms of market share - in that the trend is very clear. Intel is toast, the future is ARM. Perhaps if Andy Grove had still been at Intel things would've been very different though.
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Jay_Sankaran
8/10/2011 9:26 PM EDT
I was looking forward to a deep quantative analysis of the Intel-vs-ARM war, and was quite disappointed that it only concentrated on the 3D-vs-Planar aspect.
It is shown here that Intel has a Performance-per-unit-power lead of ~28%, even after compensating for the same (equivalent) node (22nm). This is not new, I believe there are other papers out there that give similar numbers (20-30%) for the 3D-vs-Planar comparison.
Quantitative comparisons for the other competitive parameters in the Intel-ARM battle are missing, e.g.:
* "Intel's x86 architecture is CISC. Advanced RISC machines, better known as ARM, use a RISC architecture. RISC architectures have historically given higher performance per watt than CISC in the mobile space. Can x86 bridge this gap?"
-- WHAT is % superiority of power efficiency of RISC over CISC historically? Does the specific flavor of ARM RISC provide additional advantage, and if so, what is % difference? Is it possible for x86 to bridge the gap with better designs, and how much?
* Other statements like "There are far more suppliers of ARM chips than x86 ones. Customers like competition as it keeps prices down." or "Intel has a lot more resources than players in the ARM world" are non-quantative and it would help to include some rough numbers here too.
Also, I only partially agree with the claim "The tri-gate transistor is a major engineering achievement", since 3D MOSFET geometries have been around for over a decade in semiconductor literature (Fin-FET etc.), and it is about time that it is out in production :-)
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Deepak Sekar
8/10/2011 10:00 PM EDT
@Jay:
I asked some buddies of mine at Intel if there is public literature quantifying chip power savings of their tri-gate transistor vs. their planar transistor. They said no. My colleagues in the transistor community haven't seen any of these papers either. Would appreciate your sharing these references with me, if they exist.
Reg. ARM RISC vs. Intel CISC, it is a whole new analysis. Will try to write about it on my blog one of these days...
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Jay_Sankaran
8/11/2011 12:42 AM EDT
I saw an estimate of 10-20% in David Kanter's take on Intel's 22nm 3D transistors and assumed there must be literature support for it:
http://www.realworldtech.com/page.cfm?ArticleID=RWT050511195446&p=2
Intel's 22nm Tri-Gate Transistors
"Even taking Intel’s estimates conservatively, that suggests a performance/watt advantage of 10-20% for power optimized chips versus a planar 22nm process."
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iam_girish
8/11/2011 4:08 AM EDT
I have heard that Intel processors leakage power contribution is ~10x that of ARM, and active power consumption (switching) is ~50% higher than ARM.
This tri-gate transistor technology seem to reduce only active power. Most of the mobile devices are in active mode only for 10-20% of the time, 80% of the time they are in standby/sleep - limiting leakage is key.
Power gating using high VT devices or back biasing etc.. or better architecture with low leakage/high Vt transistor is key for success in mobile industry.
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Deepak Sekar
8/11/2011 7:38 AM EDT
@Jay: I read David Kanter's article just now... it looks like guesswork to me. And he guesses 10-20%, not the 28% number I calculate above. Like I said, I know some people who worked on the tri-gate/finfet project at Intel, and they tell me they aren't aware of a scientific paper on this subject.
@iam_girish: You would choose Vdd and Vt based on your activity profile, with the result that leakage is not more than 30% of the total power... pls. check this classic paper on the subject: http://portal.acm.org/citation.cfm?id=368755 But based on the calculations above, tri-gate alone may not be enough to make up for 50% dynamic power difference and 10x leakage power difference between two chips...
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beinglass
8/11/2011 1:07 PM EDT
I agree with the author that Tri Gate is a major engineering achievement-though the idea has been around many years, but putting it in production still a big deal (BTW it took the industry 15 years to implement HKMG). Intel always leading the industry with their transistor technology like USJ, selective epi S/D, HKMG etc. All these great technical advancement keep Intel's Margin high in their core business the Microprocessor and especially the server market (Some people call Intel one trick pony).
On the other hand ARM has done wonderful by putting a great platform for low power using a plain vanilla process with a great success in the low power applications. Please check how many Ipad were sold with A4 or A5 and not an Intel's chip.
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abraxalito
8/11/2011 10:12 PM EDT
@semi111 : you've nailed it. Intel has a cash cow in their process technology, they're addicted to it. So their single trick is more bovine than equine. Those high margins make them vulnerable to disruption. Something that Andy Grove understood very well, but seems Otellini does not.
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KB3001
8/13/2011 7:03 AM EDT
Very good blog Deepak. I think it would help to split the criteria into quantitative and qualitative ones. The former can be used to make straightforward analytical techniques as you did with power consumption. The latter are more subjective in nature. I personally cannot dismiss the ~28% power advantage of Intel's trigate technology. On the other hand, the 20-50% cost advantage of ARM is also a major advantage. The real advantage however will not come from bare technology alone but from a clear advantage in the final product. The question is then: what are the key comparative advantages when it comes to products, be it in the server or mobile arena? Are there any thresholds in terms of product cost, battery life/power etc. which would make a product a success of a failure? We should then work backwards from these to see what are the corresponding thresholds in terms of bare technology.
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Deepak Sekar
8/14/2011 10:43 PM EDT
@KB3001: Your points are very valid.
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djafer
8/17/2011 12:52 AM EDT
Actually it's all very simple: Intel's problem is a that it is stuck in its own paradigma. They have grown 40years+ in the paradigm that x86 is the best architecture and that the IT world belongs to x86. Intel firmly believes this will never ever change, and behaves accordingly. But, in the IT ecosystem appeared a new beast called ARM, with new characteristics, two of the key ones being power efficiency and large licensing base. Now this new beast is starting to challenge the x86 lion, little by little depriving the lion from its "gazelle meat". Would Intel accept that x86 is a thing of the pas and start working on ARM solutions? Otellini would tell you beating his chest with his fist: Never! And that's company ego. And the bigger the ego, the harder the fall...
I wish Windows 8 for ARM had an x86 emulator in order to be able to run all the x86 legacy programs...(today Window 8 for ARM does not support backward compatibility with x86) but it seems more likely that in a couple of years most typically needed programs will have android/iOS versions of them and windows will progressively sink together with Intel. Welcome to the GoogApplarm era!
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michigan
8/19/2011 12:55 PM EDT
What I do not see from Fig.1is that at what drain voltages (Vd) the three Id/Vg curves are taken. Assuming that the upper Tri-gate blue curve and lower blue curve are taken at Vd = 1V and Vd = 50 mV, respectively, the DIBL is roughly estimated to be ~110 mV/V and the subthreshold swing (SS) is ~85 mV/decade. For FDTri-gate transistors DIBL, SS and Vt change are expected smaller. The Vt seen here is induced by large DIBL meaning the build-in source barrier is lowered by the drain voltage, resulting in lower Vt and high leakage current. Notice that ~ 0.2mA/um difference between the saturation current (Idsat) as shown by upper blue curve compared with the Idlinear shown by lower blue curve at Vd = 1V for Tri-gate are unusually small. Intel shows 32nm planar Idlinear as indicated by black curve is virtually the same as the Tri-gate Idlinear at Vd = 1V, but dose not show the corresponding Idsat for 32nm planar transistor in Fig.1. However, based on Fig. 3 of Intel’s published IEDM 2008-p943, the 32nm planar Idsat at Vd = 1V is 1.55mA/um that is significantly larger than the Idsat of 1.0mA/um for FDtri-gate transistor. Similarly, TSMC 22nm FinFET built in bulk Si substrate published in IEDM10-p600 shows Idsat equal to 1.2mA/um at Vd = 1V which is significantly smaller than Intel’s planar 32nm Idsat of 1.55mA/um.Therefore, both Intel FDTri-gate and TSMC FinFET at 22nm show the same transistor performance degradation significantly worse than Intel’s planar 32nm, and may need additional fins added in order to boost the transistor performance.
I expect the planar 22/20nm will show significantly higher transistor performance, but higher DIBL and sub-threshold leakage compared to Tri-gate and FinFET. Intel should publish its FDTri-gate device data as done for its planar 32nm to avoid the guess work
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