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"Test chip" seems to have a different meaning for every company. 1 company may ...
docdivakar
@Sanjib.Acharya: the chip does what you want it to do! Test chips are one way to ...
GlobalFoundries fabs 20-nm test chip
8/29/2011 7:15 PM EDT
SAN JOSE, Calif. – GlobalFoundries taped out a 20nm test chip using design tools from Cadence Design Systems, Magma Design Automation, Mentor Graphics and Synopsys. The test used double patterning and was implemented with each EDA partner contributing a large placed and routed design.
The test chip supported double patterning library preparation, placement, clock tree synthesis, hold fixing, routing and post-route optimization. The design flow supported extraction, static timing analysis and physical verification.
GlobalFoundries said it will make the test chip and its libraries including complete flow scripts available to customers who wish to evaluate 20nm technology.
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daleste
8/29/2011 11:07 PM EDT
Good to hear they taped out a test chip. I'll wait to see if it functions.
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Naveen.Agrawal_#3
8/30/2011 1:00 AM EDT
Hi Daleste: It seems you are in doubt about the outcome of their design? Why is that the case? Functionality can be improved as the learning curve has started with this tape-out.
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SiliconAsia
8/30/2011 9:03 AM EDT
Running test chip now while TSMC and Samsung is already running SOC test chip in 20nm?? Is GF still having an execution issues on 40nm/28nm? Are there any announced takers for gate-first 28nm technology from GF? I understand that there are some from Samsung side but have not heard any from gf side.
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Archeologist
8/30/2011 9:57 AM EDT
Test chip should not make news.
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pinhead
8/30/2011 1:25 PM EDT
With the amount of layer generation and OPC it takes for 20nm, you'd probably think that taping out a single SRAM cell is worth a mention on EE Times ;-)
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SiliconAsia
8/30/2011 11:52 PM EDT
Taping out a real SOC in 20nm then deserve a mention in NY times or wall street!!!!
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pinhead
8/31/2011 1:47 PM EDT
Haha ;-)
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Sanjib.Acharya
8/31/2011 3:06 AM EDT
Towards the end of this article it is mentioned "...available to customers who wish to evaluate 20nm technology."
What does this chip do? What is the functionality? In what package it comes?
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docdivakar
8/31/2011 7:06 PM EDT
@Sanjib.Acharya: the chip does what you want it to do! Test chips are one way to validate a given higher technology node but that is 1/4 of the story. Real design with memory / logic / FPGA will of a myriad of problems that a developer of an ASIC will have to hand-hold with GloFo. I am not discounting the packaging challenges either with 20nm process.
Tabula has already demonstrated 22nm FPGA so this news release is no way getting the attention or hype if at all intended!
Dr. MP Divakar
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CACHE
9/1/2011 8:19 AM EDT
"Test chip" seems to have a different meaning for every company. 1 company may describe Test Chip as a mask field full of test structures, while another could call a SOC w/ SRAM, logic, etc their "Test Chip". The article doesn't clarify the details of this announcement, I think people are making their own implications which may or may not be accurate.
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